Test device for signaling and waveform generation and monitoring Number:7,155,362 from the United States Patent and Trademark Office (PTO) owispatent

Title: Test device for signaling and waveform generation and monitoring

Abstract: A system for generating a signal for testing a relay is provided. The system includes a plurality of argument vector arrays, each defines a digital signal for testing the relay. Each of the argument vector arrays includes a plurality of argument vectors and each argument vector includes a plurality of arguments. The system includes a plurality of waveform generators to generate a plurality of signal components. Each waveform generator generates the signal component based on the argument vectors contained by a selected one of the plurality of argument vector arrays. The system also includes a merge component to combine the signal components to produce the digital signal for testing the relay.

Patent Number: 7,155,362 Issued on 12/26/2006 to Edwards,   et al.

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Inventors:	Edwards; Michael (McKinney, TX), Elzy; Terry L. (Frisco, TX), Maahs; Michael (Dallas, TX), Miller; Marvin G. (Carrollton, TX)
Assignee:	AVO Multi-Amp Corporation (Dallas, TX)
Appl. No.:	10/875,007
Filed:	June 23, 2004

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Current U.S. Class:	702/124 ; 702/108
Current International Class:	G01M 19/00 (20060101)
Field of Search:	702/69,70,115,118 708/272 324/124-126

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References Cited [Referenced By]

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U.S. Patent Documents

	4464628		August 1984		Nozawa
	4689570		August 1987		Ohgaki et al.
	5029120		July 1991		Brodeur et al.
	5710513		January 1998		March
	5748001		May 1998		Cabot
	6396279		May 2002		Gruenert
	6850073		February 2005		Elms et al.

Other References

Bela Deak, et al., Protective Relay Test Device, Filing Date--Jun. 23, 2004, Application No. 10/874,458, Specification (76 pgs.) and Drawings (18 sheets). cited by other . Aaron C. Klijn, et al., Protective Relay Test Device Having a Hand-Held Controller, Filing Date--Jun. 23, 2004, Application No. 10/875,017, Specification (74 pgs.) and Drawings (18 sheets). cited by other . Aaron C. Klijn et al., Programmable System for Device Testing and Control, Filing Date--Jun. 23, 2004, Application No. 10/874,969, Specification (79 pgs.) and Drawings (18 sheets). cited by other.

Primary Examiner: Suglo; Janet L
Attorney, Agent or Firm: Conley Rose, P.C. Brown, Jr.; J. Robert

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Claims

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What is claimed is:

1. A system for generating a signal for testing a relay, comprising: a plurality of argument vector arrays each operable to define a digital signal for testing the relay, each argument vector array including a plurality of argument vectors, wherein each argument vector includes a plurality of arguments; a plurality of waveform generators operable to generate a plurality of signal components, each waveform generator generates the signal component based on the argument vectors contained by a selected one of the plurality of argument vector arrays; and a merge component operable to combine the signal components to produce the digital signal for testing the relay.

2. The system of claim 1 wherein the waveform generators are further operable to generate a plurality of orthogonal basis functions as the signal components.

3. The system of claim 1 wherein one of the plurality of waveform generators is further defined as a first sine waveform generator operable to generate a sine wave signal component and wherein the argument vector associated with the first sine waveform generator includes an amplitude argument, a frequency argument, and a phase argument.

4. The system of claim 3 wherein the waveform generators include a plurality of sine waveform generators, each sine waveform generator operable to generate an additional sine wave signal component, and wherein the argument vectors associated with the additional sine waveform generators includes an amplitude argument, a frequency argument, and a phase argument.

5. The system of claim 4, wherein the frequency argument is a harmonic frequency associated with the first sine waveform generator.

6. The system of claim 4, wherein the frequency argument is unrelated to the frequency associated with the first sine waveform generator.

7. The system of claim 4 wherein the first sine wave signal component and the additional sine wave signal components are each calculated as a discrete time function using a series expansion method based on looking up a first approximation of the discrete time function at a discrete time point.

8. The system of claim 4, further including an exponential damping component wherein the digital signal is multiplied by a damping coefficient, wherein the damping coefficient is calculated as the integer exponentiation of a basis number, the basis number representing a positive real number less than 1, the basis number contained at least in each related argument vector array.

9. The system of claim 8 wherein the exponential damping component is selectable such that the damping coefficient is multiplied to the digital signal only when the exponential damping component is selected.

10. The system of claim 4 further comprising a digital low pass filter component operable to digitally low pass filter the digital signal, the digital low pass filter component includes a time constant.

11. The system of claim 9 further comprising a digital low pass filter component operable to digitally low pass filter the digital signal, the digital low pass filter component includes a time constant.

12. The system of claim 10 further including a digital feedback component to promote correcting an output.

13. The system of claim 10 further including an analog feedback component to promote correcting an output.

14. The system of claim 10 further comprising: a digital feedback component operable to sample an output and communicate with the merge component to promote correcting to a desired output; and an analog feedback component operable to sample the output and to further promote correcting the desired output.

15. The system of claim 1 wherein one of the plurality of waveform generators is further defined as a half-sine waveform generator, and wherein the argument vector associated with the half-sine waveform generator includes an amplitude argument, a frequency argument, and a phase argument.

16. The system of claim 1 wherein one of the plurality of the waveform generators is further defined as a square waveform generator, and wherein the argument vector associated with the square waveform generator includes a amplitude argument, a frequency argument, and a phase argument.

17. The system of claim 1, wherein one of the plurality of the waveform generators is further defined as a direct current offset waveform generator, and wherein the arguments associated with the direct current offset waveform generator include an amplitude argument.

18. The system of claim 1, further including a digital low pass filter component operable to digitally low pass filtering the digital signal, and wherein the digital low pass filter component includes a time constant.

19. A method for generating a signal for testing a relay, including: defining a first group of arguments; generating, by a relay test device, one or more component signals based on the first group of arguments; summing, by the relay test device, the component signals to create a combined signal; and amplifying, by the relay test device, an output signal based on the combined signal to generate the signal for testing the relay.

20. The method of claim 19 further including monitoring a feedback signal associated with the signal generated for testing the relay, and wherein the output signal is further based on the feedback signal.

21. The method of claim 19 wherein at least some of the component signals are generated from orthogonal basis functions.

22. The method of claim 21 wherein the orthogonal basis functions are sine functions.

23. The method of claim 19 wherein generating the component signals involves calculating a value of the component signals during a clock interrupt service routine.

24. The method of claim 23 further including: defining a second groups of arguments; selecting the first group of arguments for generating the component signals during a first execution of the clock interrupt service routine; and selecting the second groups of arguments for generating the component signals during a second execution of the clock interrupt service routine.

25. The method of claim 19 further including exponentially dampening the combined signal to create a dampened combined signal, and wherein the output signal is based on the dampened combined signal.

26. The method of claim 19 further including low-pass filtering the combined signal to create a low-pass filtered combined signal and wherein the output signal is based on the low-pass filtered combined signal.

27. The method of claim 19 wherein the signal is generated by a plurality of modular signal generation components each comprising: a signal generator to generate the one or more component signals; a processor in communication with the signal generator regarding signal generation; an amplifier to amplify the signal generated by the signal generator; and a power supply to provide power to the signal generator.

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Description

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CROSS-REFERENCE TO RELATED APPLICATIONS

This application is related to U.S. patent application Ser. No. 10/874,969 entitled "Programmable System for Device Testing and Control", and U.S. patent application Ser. No. 10/875,017 entitled "Protective Relay Test Device Having a Hand-Held Controller", and U.S. patent application Ser. No. 10/874,458 entitled "Protective Relay Test Device", all filed on even date herewith and all of which are incorporated herein by reference for all purposes.

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR DEVELOPMENT

Not applicable.

REFERENCE TO A MICROFICHE APPENDIX

Not applicable.

FIELD OF THE INVENTION

The present disclosure is directed to test equipment, and more particularly, but not by way of limitation, to a system and method for testing protective electrical power relays.

BACKGROUND OF THE INVENTION

The electrical power system in the United States generates three-phase alternating current (AC) electrical power. Each power phase is 120 degrees out of phase, plus or minus, with the other two power phases. The voltage of any phase oscillates sinusoidally between positive voltage and negative voltage. It happens that three-phase power distribution provides an acceptable compromise between electrical generation and distribution efficiency and the expense and complexity of power distribution equipment.

It is more efficient to transmit electrical power at high voltage levels than at low voltage levels. Electrical power is generated as three-phase AC power at moderate voltage levels in the 12 thousand volt (kV) to 25 kV range. The voltage level is stepped up to the 110 kV to 1000 kV range using a transformer for transmission over long transmission lines, hence minimizing transmission line power loss. The transmission line voltage is stepped down, using a transformer at a substation, to the 12 kV to 35 kV range for local distribution. The local distribution voltage level is further stepped down through one or more transformer stages to provide 120 volt AC power to the home and office. Special accommodations may be made for manufacturing plant electrical power consumers.

Switchgear is employed to control the transmission systems. The switchgear may include circuit breakers, fuses, switches, and relays. Electrical power distribution protective relays, hereinafter referred to simply as "relays," monitor a variety of electric power distribution parameters and control circuit breakers based on the state or condition of the electric power distribution parameters. For example, if too much current is being provided to a local distribution line, a relay may command a circuit breaker or switch gear to open, thus interrupting the supply of electrical power to that local distribution line. Current, voltage level, frequency, phase, and other parameters may be monitored by relays.

Relays vary in complexity from electro-mechanical devices monitoring a single parameter to microprocessor controlled relays capable of monitoring many independent parameters concurrently. The relays are capable of changing their behavior when reprogrammed for monitoring various characteristics of a power distribution system. For safe and reliable operation of the power distribution system it is necessary to thoroughly test relays in the manufacturer's plant, prior and upon installation in the power distribution system, and at periodic intervals after installation. Failures of the power distribution system, such as the power blackout in the northeastern United States and southeastern Canada in 2003, can result in significant economic losses and inconvenience, and perhaps danger to those requiring special medical services dependent on electrical power distribution.

Testing of relays may be accomplished by emulating theoretical fault characteristics of a power distribution or generation system, thereby validating design elements associated with protection systems on a power distribution or generation system. This emulation consists of various parameter characteristics associated with the power distribution system during a fault. Fault conditions, generated through emulation, are therefore applied to the relay, and expected results are anticipated, validated or settings corrected for correct operation when the relay is applied in an actual power distribution system.

SUMMARY OF THE INVENTION

According to one embodiment, the present disclosure provides a system for generating a signal for testing a relay. The system includes a plurality of argument vector arrays each is operable to define a digital signal for testing the relay. Each argument vector array includes a plurality of argument vectors and each argument vector includes a plurality of arguments. The system includes a plurality of waveform generators that are operable to generate a plurality of signal components. Each waveform generator generates the signal component based on the argument vectors contained by a selected one of the plurality of argument vector arrays. The system also includes a merge component to combine the signal components to produce the digital signal for testing the relay.

In one embodiment, a method is provided for generating a signal for testing a relay. The method includes defining a first group of arguments, and generating, by a relay test device, one or more component signals based on the first group of arguments. The method includes analyzing, by the relay test device, the component signals to create a combined signal, and amplifying, by the relay test device, an output signal based on the combined signal to generate the signal for testing the relay.

In one embodiment, a system is provided for playing back a digital signal by a relay test device to test a relay. The system includes a first digital recording at a first frequency, a second digital recording at a second frequency, and a clock. The clock has a frequency based on a parameter such that to play the first digital recording the parameter is based on the first frequency and the clock is operable to generate interrupts at the first frequency, and further such that to play the second digital recording the parameter is based on the second frequency and the clock is operable to generate interrupts at the second frequency. The system also includes a playback component that uses the clock interrupts generated and based on the parameter to play back the first digital recording at the first frequency and the further to play back the second digital recording at the second frequency.

In another embodiment, the present disclosure provides a system for generating a digital signal. The system includes a digital recording based on a sampling frequency, and a playback component to output a value from the digital recording during a clock interrupt service routine. A clock interrupt generator is operable to output a clock interrupt at a frequency based on a parameter, and a processor component is operable to respond to the clock interrupt by invoking the clock interrupt service routine.

These and other features and advantages will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings and claims.

BRIEF DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present disclosure and the advantages thereof, reference is now made to the following brief description, taken in connection with the accompanying drawings and detailed description, wherein like reference numerals represent like parts.

FIG. 1 is a block diagram of a relay test device according to one embodiment.

FIG. 2 is a block diagram of another embodiment of the relay test device.

FIG. 3 is a block diagram of a controller module of the relay test device.

FIG. 4 is a flow chart illustrating one embodiment of a method for using the relay test device.

FIG. 5 is a flow chart illustrating another embodiment of a method for using the relay test device.

FIG. 6 is a flow chart illustrating another embodiment of a method for using the relay test device.

FIG. 7a is a flow chart illustrating another embodiment of a method for using the relay test device.

FIG. 7b illustrates another method for employing the relay test device according to another embodiment.

FIG. 8 is a block diagram of a software and firmware installation system for the several embodiments of the relay test device.

FIG. 9 is a flow chart illustrating a method for using a system for installing software and/or firmware versions in the relay test device.

FIG. 10a is a block diagram of one embodiment of a signal generator for use in the relay test device.

FIG. 10b is a graph of a constant power output according to an embodiment of the present disclosure.

FIG. 11 is a block diagram of several functional components within the signal generator of the relay test device.

FIG. 12 is a block diagram of the signal generation functional component within the signal generator of the relay test device.

FIG. 13 is a block diagram of a digital recording playback system employing an adaptive clock interrupt.

FIG. 14 is a flow chart illustrating a method for using a digital recording playback system employing an adaptive clock interrupt.

FIG. 15 is a block diagram of a touch view interface for use with the relay test device.

FIG. 16 depicts one embodiment of a graphical display of the touch view interface.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

It should be understood at the outset that although an exemplary implementation of one embodiment of the present disclosure is illustrated below, the present system may be implemented using any number of techniques, whether currently known or in existence. The present disclosure should in no way be limited to the exemplary implementations, drawings, and techniques illustrated below, including the exemplary design and implementation illustrated and described herein.

Relays may be tested employing a relay test device containing a powerful power supply and amplifier and employing a separate personal computer (PC) to control the relay test device. The relay test device may be relatively dumb and may depend upon the separate PC to provide the intelligence needed to test relays. Unfortunately PCs may not operate effectively in the harsh field conditions where relays are installed. High levels of electromagnetic interference in the field may damage PCs or interfere with the reliable functioning of PCs. Dirt and grit may readily infiltrate the mechanical workings of the PC in the field. Industrial use of standard PCs can result in damage to the PC from excessive handling, and exposure to environments not well suited for standard office PC equipment, thereby shortening the lifespan of the PC.

Electrical power distribution transducers, for example, current loop transducers, which provide an indication of the current flowing through a wire or transmission line, are typically tested using an independent test set operated under the control of the separate PC.

Also, a relay test operator typically must have relatively advanced knowledge of relays and electrical power distribution to test the relays employing the relay test device and the separate PC. Personnel with advanced knowledge may be in limited supply, increasing the electrical power company's labor cost due to competition to hire limited skilled personnel or delaying testing.

In one or more of the disclosed embodiments, the present disclosure describes an improved relay test device which combines, in one box, the intelligence necessary to operate independent of the separate PC and to support automated tests, integrates in the same box a transducer testing capability, and includes a number of other new features and capabilities.

Programmable Relay Test Device

Turning now to FIG. 1, a block diagram of an embodiment of a relay test device 10 is depicted. The relay test device 10, includes a controller 2, a signal generator module 4 which may include one or more signal generators, a plurality of signal amplifiers 6--a first signal amplifier 6a, a second signal amplifier 6b, and a third signal amplifier 6c--and a power supply 8. A user interface (UI) 20 is coupled to the controller 2 and provides command inputs and displays test results. In the present embodiment, the controller 2, the signal generator module 4, the signal amplifiers 6, and the power supply 8 may be retained by an enclosure 22. The enclosure 22 may provide shielding from electromagnetic interference (EMI), help control cooling of the system electronics comprised of the controller 2, the signal generator module 4, the signal amplifiers 6, the power supply 8 and provide environmental protection. In some embodiments the enclosure 22 may not completely enclose the controller 2, the signal generator module 4, the signal amplifiers 6, and the power supply 8. The enclosure 22 may be open on one or more sides. The enclosure 22 may be formed of various materials, including metal or polymeric materials. The enclosure 22 may be formed of expanded metal material. The enclosure 22 may also be referred to as a chassis, an equipment cabinet, a shell, or a body.

A relay under test 24 is depicted as connected to the output of the first signal amplifier 6a. In some test scenarios, the relay under test 24 may be connected to the relay test device 10 in other manners, and the connection between the relay under test 24 and the relay test device 10 may include a plurality of wires or cables. Some relays now provide an Ethernet interface, and the relay test device 10 may communicate with the relay under test 24 via an Ethernet connection.

The controller 2, in this embodiment, may include a central processor unit (CPU), which may be composed of one or more digital signal processors (DSPs), microprocessors (uPs), microcontrollers (uCs), field programmable gate arrays (FPGAs), complex programmable logic devices (CPLDs), programmable logic devices (PLDs), and/or application specific integrated circuits (ASICs). The CPU of the controller 2 may employ an operating system, such as a Real Time Operating System (hereinafter referred to as "RTOS") or a standard non-deterministic operating system.

The controller 2 may contain a plurality of memory devices including one or more random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), and Flash memory or a combination thereof. The controller 2 may have multiple interfaces, collectively referred to as input/output (I/O) 7, including but not limited to any communications method, such as an Ethernet interface, a wireless interface, an IEEE-1394 interface, an IEEE-488 interface, a RS-232 interface, a RS-422 interface, a printer interface, a universal serial bus interface (USB), a proprietary intercommunications interface, a plurality of programmable digital inputs, a plurality of programmable digital outputs, one or more transducer inputs, and other interfaces. These interfaces permit the relay test device 10 to communicate with other devices, for example via an Internet, via an intranet, via wireless communications, and via satellite or other means to other data-oriented systems, such as a PC or another controller 2 on a separate system for particular methods of test or data acquisition.

The controller 2 may store, in one or more of the memory devices, such as memory location 5, a test procedure or test program that the controller 2 executes to sequence the relay test device 10 through the steps of testing the relay under test 24. The controller 2 also may store, in one or more of the memory devices, a test procedure or test program that the controller 2 executes to test a transducer, for example to test a current loop transducer using the transducer input. The controller 2 may communicate with the relay under test 24, for example via Ethernet, to request from the relay under test 24 information about the settings or control configuration of the relay under test 24 and to command or reprogram the relay under test 24 to a group of settings or control configuration sent to the relay under test 24 by the controller 2. The controller 2 is in communication with the signal generator module 4 and controls the signal generator module 4 to produce desirable test signals. The controller 2 monitors the relay under test 24 throughout the test, determines a result of the test of the relay under test 24, and sends the result to the UI 20 to be displayed.

The controller 2 may log all the results, test procedure actions and state changes of the relay, including initial settings, commonly termed "as found settings," of the relay under test 24 and any reprogramming settings sent to the relay under test 24, to memory where it may be accessed at a later time. The access of this data may be accomplished using one of the interfaces of the controller 2, for example over Ethernet or over wireless or other typical communications means to the Internet, or the relay test device 10 may be transported to a laboratory, office, or shop to download one or more test logs for further analysis. The test logs make it possible to accurately reproduce a test run, even if the test system default values are changed. The relay test device 10 may be in communication with other equipment employed in testing the relay under test 24, and the relay test device 10 may store, such as in the system memory, information provided by the other equipment.

The signal generator module 4 provides a test signal to each of the signal amplifiers 6. Each signal amplifier 6 boosts the test signal to a level which is useful for outputting to test the relay under test 24. In one embodiment, the signal amplifier 6 may produce a 150 to 200 volt-amp (VA) power level. In other embodiments, the signal amplifier 6 may be rated to produce maximum power outputs in the range from only a few VA to several thousand VA, depending on the type and application of the protection relay being tested. Typically, signal generators used for communications and bench top electronic circuit design work provide low level signals, such as 1 to 12 volts into an impedance of 50 to 75 ohms. Signal generators used in protection relay testing typically utilize power levels greater than this, and, in some embodiments, may be focused on 50 and 60 Hz line rates, utilizing voltages of 5 volts to 300 volts into impedances that vary from less than one-tenth ohm to as much or more than 600 ohms. In addition, signal generators used in bench top electronic circuit design are usually not designed to drive a wide variety of loads, such as presented by various protective relay instruments, nor provide the wide range of voltages and currents required. Protective relay testing may use signal generators that are oriented towards abrupt changes and arbitrary waveform generation mimicking abrupt faults applied to a protection relay, although subtle changes and constant signals are used in various forms of protective relay testing, such as with testing phase-related protection relays and generation system protection relays. The power supply 8 provides direct current (DC) power to each of the signal amplifiers 6. The power supply 8 receives alternating current (AC) power from the AC power mains (not shown) within the relay test device 10. The AC power mains receive power from, for example, a power chord and plug connected to external utility power. The controller 2 and the signal generator module 4 may receive DC power from the power supply 8 or may receive power from one or more other DC power supplies (not shown).

The signal generator module 4 includes a central processor unit (CPU) which may be composed of one or more DSPs, uPs, uCs, FPGAs, CPLDs, PLDs, and/or ASICs. The signal generator module 4 may include one or more memories including RAM, ROM, EPROM, EEPROM, and Flash memory or a combination thereof. The signal generator module 4 may generate complex signals from waveform components using a computer program, software, or firmware stored in one or more memories. The signal generator module 4 may playback periodic waveforms stored in data tables, may playback a digital fault recording (DFR) recorded by or of a relay, or may playback a streaming digital data recording or real-time stream from another source such as an external signal data reproduction system such as a PC or data recorder via means similar to MP3 streams utilized on the Internet for audio streaming broadcasts today. These processes are discussed in more detail hereinafter when discussing another embodiment of the relay test device 10.

The relay test device 10 provides a stand-alone test set which may be used by personnel with relatively limited knowledge and experience of relays and electrical power distribution. The relay test device 10 may simplify the complex field test procedures associated with other test devices down to procedures involving pointing and clicking by field service personnel which causes complete tests to run and test results to be reported and stored. In one embodiment, the relay test device 10 may support initiating tests from and displaying and analyzing results on a general purpose computer system, such as a personal computer or a workstation, for example in a manufacturer's relay test shop, or via a display directly associated and a part of the relay test device 10. In some embodiments, a relay status monitor feedback 3 is operable to communicate with a timer 9.

Turning now to FIG. 2, a block diagram of another embodiment of the relay test device 10 is depicted. While the embodiment of the relay test device 10 depicted in FIG. 1 provides many of the same advantages and capabilities of the embodiment of the relay test device 10 depicted in FIG. 2, the embodiment depicted in FIG. 1 contains a single point of failure in the signal generator module 4 and a single point of failure in the power supply 8. For example, if the signal generator module 4 fails, the embodiment of the relay test device 10 depicted in FIG. 1 may be unavailable for continued testing. Similarly, if the power supply 8 fails, the embodiment of the relay test device 10 depicted in FIG. 1 cannot continue testing. The embodiment of the relay test device 10 depicted in FIG. 2 removes many of the critical single points of failure associated with the architecture of the relay test device 10 depicted in FIG. 1, by utilizing redundant elements in the areas of the design most prone to stress induced failures.

The relay test device 10 includes a backplane 12, a controller module 14, and a plurality of VI (voltage and current) generators 16--a first VI generator 16a, a second VI generator 16b, a third VI generator 16c, and a VI generator 16d. In an embodiment, the VI generators 16, which may also be referred to as signal generators, communicate with the controller module 14 over a low voltage differential signaling (LVDS) data bus 18 and employ an error checking and correction protocol to assure reliable communications. The error checking and correction protocol may employ parity bits, packet delimiters or markers, packet receipt confirmation handshakes, cyclic redundancy checking (CRC), and/or other well known methods of verifying communications. In another embodiment, however, the LVDS bus may not be employed, and alternative communication buses may be employed. In another embodiment the error checking and correction protocol is not employed. In some embodiments, either more or fewer VI generators 16 may be installed in the relay test device 10.

The controller module 14 may communicate with a user interface (UI) 20 via a connector on the backplane 12. In an alternate embodiment, the controller module 14 may communicate with the UI 20 without routing through the backplane 12. In an embodiment, the UI 20 communicates with the controller module 14 using LVDS. In the embodiment depicted in FIG. 2, the LVDS data bus 18 is shown separately from the backplane, whereas in another embodiment, the LVDS data bus 18 may be integrated within the backplane. The controller module 14 employs an error checking and correction protocol to assure reliable communication with the UI 20. The error checking and correction protocol may employ parity bits, packet delimiters or markers, packet receipt confirmation handshakes, CRC, and/or other well known methods of verifying communications. In another embodiment, however, LVDS may not be employed. In another embodiment the error checking and correction protocol is not employed. The controller module 14 receives DC power from a DC power supply (not shown).

The relay under test 24 is depicted as connected to the output of the second signal generator 16b. In some test scenarios, the relay under test 24 may be connected to the relay test device 10 in other manners, and the connection between the relay under test 24 and the relay test device 10 may include a plurality of wires or cables.

The controller module 14 may be referred to as a digital module. The controller module 14 may connect to at least a portion of the I/O 7 directly and may connect to other interfaces via the backplane 12. The VI generators 16 may be referred to as VIGENs, because they may generate voltage (V) and current (I) signals. In the present embodiment, the backplane 12, the controller module 14, the VI generators 16, and the LVDS data bus 18 are retained within the enclosure 22. In some embodiments the enclosure 22 may not completely enclose the backplane 12, the controller module 14, the VI generators 16, and the LVDS data bus 18.

The backplane 12 provides connectivity to receive a plurality of inputs and to transmit a plurality of autonomous outputs. The controller module 14 and the VI generators 16 connect to the inputs and outputs, each of which will be discussed hereafter in association with the controller module 14 and the VI generators 16.

Turning now to FIG. 3, a block diagram of the controller module 14 is depicted. The controller module 14 includes an embedded PC CPU 100, a timer CPU 102, and a first LVDS transceiver 104. The embedded PC CPU 100 may comprise one or more DSPs, FPGAs, PLDs, CPLDs, ASICs, uPs, uCs, or a combination thereof. The embedded PC CPU 100 is in communication with memory 105, the LVDS transceiver 104, input/output devices, and network connectivity devices. The input/output devices and network connectivity devices may be collectively referred to as I/O 7. Some of the I/O 7 depicted in FIG. 3 may route through the backplane 12 while some of the I/O 7 may directly connect to interfaces or external devices. In an embodiment, the embedded PC CPU 100 may be in communication with a secondary memory device, for example, a magnetic disk storage device, an optical disk storage device, another type of media storage device employing an alternate media, or a memory device represented as a disk storage device to the embedded PC CPU 100. Memory devices, such as a memory 105 and a flash disk I/O 103, may be located on the controller module 14 and accessible to the embedded PC CPU 100 and the timer CPU 102. The memory devices may include such as RAM, ROM, EPROM, EEPROM, and Flash memory or a combination thereof. In an embodiment, the controller module 14 is provided with significant memory, such as 64 megabytes of memory. The controller module 14 may store test parameters, multiple versions of software and firmware, and multiple versions of an operating system.

In an embodiment, the controller module 14 is a single board computer (SBC). The term SBC is an industry standard term for a self-contained computer system. An SBC may contain a CPU (such as an X86, ARM, Risc or other type of main processing unit) / memory for random access operation typically utilized by the operating system and the applications, storage of data such as disk on a chip (DOC) compact flash, or microdrive, as well as standard interfaces such as IDE to connect to the compact flash, microdrive or standard externally mounted drive you see in a standard desk top PC. It usually also contains standard interfaces, such as RS-232, Digital I/O, PC104 and PC104 Plus interfaces, and often contains USB, Ethernet, keyboard, mouse and video display interface capabilities.

The input/output devices may include one or more RS-232 serial data ports, RS-422 serial data ports, IEEE-488 ports, printer interfaces, USB interfaces, Ethernet ports, and EPOCH high current interface ports. Some of these input/output devices may be connected as I/O 7 directly to the PC CPU 100. The input/output devices may also include one or more clock inputs, clock outputs, transducer inputs, touch view interfaces, a plurality of programmable digital inputs, and a plurality of programmable digital outputs. In an embodiment, the programmable I/O 107 may be connected to the timer CPU 102. These interfaces permit the relay test device 10 to communicate with other devices, for example via an Internet, via an intranet, via wireless communications, and via satellite. In an embodiment, the embedded PC CPU 100 employs the VxWorks.RTM. operating system.

The embedded PC CPU 100 executes software or firmware operable to install versions of software and of firmware, to manage the UI 20, to receive and store a definition of a test procedure, and to manage all the resources of the relay test device 10 during testing activities. The embedded PC CPU 100 executes programs that test the relay under test 24. The embedded PC CPU 100 also executes programs that test transducers, for example current transducers. The relay test device 10 may store a plurality of user profiles, for example in the memory on the controller module 14. The user profiles include individual user preferences and may include user specific cues, such as reminders of in-progress activities or things to do. User preferences may include display preferences, for example displaying vectors in the range from -180 degrees to +180 degrees versus displaying vectors in the range from 0 degrees to 360 degrees. The user profile may be stored with test data so that the test of the relay under test 24 may be completely re-created.

The UI 20 is a ruggedized input/output device based on a video display, touch screen and controller, and a CPLD for communications with the embedded PC CPU 100, a user control dial and enclosure. In the preferred embodiment, the embedded PC CPU 100 provides the intelligence and processing capabilities for the UI 20. As such, the embedded PC CPU 100 determines the content of the display to be presented by the UI 20 and sends the content of the display to the UI 20. The UI 20 receives a control input and sends user initiated control input to the embedded PC CPU 100. The embedded PC CPU 100 processes the control input from the UI 20, including navigating through a hierarchy of displays. In an alternate embodiment, however, the UI 20 may provide the intelligence and processing power to navigate through menus and to generate the content of the display. In an alternate embodiment the UI 20 may contain and execute test procedures and send test control commands to the VI generators 16 via the controller module 14 or via another communication path. A touch view interface (TVI), a particular embodiment of the UI 20, will be discussed in greater detail hereinafter.

The embedded PC CPU 100 may receive the definitions of test procedures through a network connection, for example an Ethernet connection to a local area network (LAN), and stores the definitions of test procedures in memory, such as in RAM or in nonvolatile memory such as flash memory. The relay test device 10 may receive definitions of test procedures in an office LAN environment, for example. Alternately, the relay test device 10 may receive definitions of test procedures in the field, for example via an Ethernet connection to a laptop PC having wireless connectivity to an Internet or to a mobile phone having wireless connectivity to an Internet. In an embodiment, the embedded PC CPU 100 may receive the definitions of test procedures through a different connection, such as through a serial interface or an USB interface. Numerous other means of receiving definitions of test procedures via various interfaces are within the scope of the present disclosure and will readily suggest themselves to one skilled in the art.

The embedded PC CPU 100 may control the execution of test sequences by executing a generic test loop, customized by reading or analyzing the definition of a test procedure stored in the controller module 14. Test sequence operations may include sending data files to the VI generators 16, configuring the VI generators 16, responding to the programmable digital inputs, and driving the programmable digital outputs. Test sequence operations may include interrogating the relay under test 24 to determine the initial or "as found" settings of the relay under test 24, storing the as found settings of the relay under test 24, changing the settings of the relay under test 24. Test sequences may also include testing the relay under test 24, determining the status of the relay under test 24, furthermore determining the success or failure of the test of the relay under test 24, and restoring the as found settings into the relay under test 24. The test sequence operations may include changing the settings of the relay under test 24 to factory settings as a precondition for running the test.

The embedded PC CPU 100 generates a log of the execution of test sequences, and of inputs, for example the programmable inputs from the timer CPU 102. The test sequence operations may include interrogating a relay to determine the settings of the relay under test 24, testing the relay according to a specific or generic test procedure which is customized by using the settings of the relay under test 24--this may be termed testing the relay under test 24 according to its settings or "as found" settings--and determining success or failure of the test.

The embedded PC CPU 100 may log the actions of the test sequences, the inputs, and the state changes of the relay under test 24 to memory 105. Thereafter, one or more test logs may be downloaded over one of the interfaces of the controller module 14. Alternately, the relay test device 10 may be transported to a laboratory, office, or shop to download one or more test logs for further analysis. The test logs may be printed out by a printer connected to the printer interface or to the USB interface. The test logs make it possible to accurately reproduce a test run, even if the test system default values are changed. The relay test device 10 may be in communication with other equipment employed in testing the relay under test 24, and the relay test device 10 may store in the test logs information provided by the other equipment.

Turning now to FIG. 4, a method for using the relay test device 10 is depicted. At block 200 a test procedure is received and stored in the relay test device 10. The test procedure may have been defined or programmed by personnel skilled with protection relay systems and equipment and/or electrical power distribution technology and regulations. The test procedure describes a series of actions for the relay test device 10 to take to test the relay under test 24. The test procedure may include data, such as a DFR or a data table representing a periodic waveform. Alternately, data may be received by the relay test device 10 in a separate step after or before block 200. In an embodiment, the test procedure may be expressed in an advanced visual test software (AVTS) proprietary programming language. Single AVTS commands are expanded into several relay test system (RTS) commands, where RTS is another proprietary programming language. Single RTS commands are expanded into several commands to the VI generator 16 executable by the VI CPU 450 depicted in FIG. 10a. The commands to the VI generator 16 may be, for example, assembly language commands in the native language of the DSP 464. In another embodiment, the commands to the VI generator 16 may be based on a proprietary language scheme optimized for reducing data volume on the LVDS data bus 18, promoting test signal generation by desired characteristics of a test signal, such as relative phase to other VI generators 16, reference to an internal or external clocking source, change of frequency, change of amplitude, DC offset or voltage offset, start and stop control of the signals.

In an embodiment, the relay test device 10 may receive the test procedure or test procedure updates through communication with external devices, for example through Ethernet communication with a laptop computer. The test procedure may be downloaded to the relay test device 10 from a laptop computer in a lab, office, or shop, and the relay test device 10 may be transported thereafter to the field to test relays. In another embodiment, the relay test device may be temporarily resident at a remote location, such as an electrical substation location, and receive the test procedure updates downloaded through the Wide Area Network (WAN) from a PC or intranet or Internet or other type of file transfer capable data storage and retrieval site. In another embodiment, the relay test device 10 may receive the test procedure originating from a memory device such as a flash memory card integral to the embedded PC CPU 100, an optical disk inserted into an optical disk reader, a magnetic disk inserted into a magnetic disk reader, or an alternate media inserted into an alternate media storage device which may be integral to the relay test device 10.

The method proceeds to block 202 where the relay test device 10 is connected to the relay under test 24, the test procedure is started or initiated, and the relay test device 10 performs an action of the test procedure. A field operator without special knowledge of relays or electrical power distribution technology or regulations may transport the relay test device 10 to the field, connect the relay test device 10 to the relay under test, and initiate the test procedure. In an embodiment, the UI 20 may provide a depiction of a schematic drawing or a bit map digital image of, for example, a relay and patch cables connecting to the relay which facilitates connecting the relay under test 24 to the relay test device 10. The embedded PC CPU 100 may read an instruction of a computer program encoding the test procedure and, based on this instruction, command one or more VI generators 16 to output a test signal to the relay under test 24. Alternately, the embedded PC CPU 100 may command the timer CPU 102 to output a state on one of the programmed outputs. The VI generator 16 outputs a test signal to the relay under test 24 and/or the timer CPU 102 outputs a state on one of the programmed outputs to the relay under test 24.

The method proceeds to block 204 where the relay test device 10 monitors the relay under test 24. The relay test device 10 may monitor a plurality of indications of a state of the relay under test 24. In some embodiments, the relay test device 10 generates a log of the test actions and the indications of the state of the relay under test 24. The method proceeds to block 206 where the method returns to block 202 if the test of the relay under test 24 is incomplete. By looping through block 202 and block 204 the relay test device 10 sequences through the test procedure and tests the relay under test 24. In some test procedures, the relay test device 10 may generate a voltage or current signal which the relay test device 10 sends to the relay under test 24, such as the voltage and current signals which the VI generators 16 are capable of generating.

When the test of the relay under test 24 is complete, the method proceeds to block 208 where the relay test device 10 analyzes the final state of the relay under test 24 to determine whether the relay under test 24 passed or failed the test. The method proceeds to block 210 where the relay test device 10 reports the test result to the UI 20. In an embodiment, the log of the test actions and the indications of the relay may be stored in a file in memory 105 or memory storage device 103, and the file may be transferred to an external device, for example to a laptop computer via Ethernet communications. The log may be analyzed in more detail at a later time, for example in a corporate office or laboratory for the purpose of verifying pass or fail test results.

Turning now to FIG. 5, a method for using the relay test device 10 according to another embodiment is depicted. The method depicted in FIG. 5 is substantially the same as the method depicted in FIG. 4, with differences noted below. It is understood that after block 250 and before block 252 a field operator without special knowledge of relays or electrical power distribution technology or regulations may transport the relay test device 10 to the field, connect the relay test device 10 to the relay under test 24, and initiate the test procedure. At block 252 the relay test device 10 reads the initial settings, initial configuration parameters, or initial adjustments of the relay under test 24 from the relay under test 24. The relay test device 10 stores the initial settings otherwise known as "as found" data of the relay under test 24.

The method proceeds to block 254 where the relay test device 10 writes test settings to the relay under test 24. This action may be referred to as reprogramming the relay under test 24. In some cases, the test settings may be factory settings specified for the relay under test 24, or special test settings which ensure specific relay elements operate as expected, without influence from other relay test device 10 elements not of interest for the specific test applied. The method loops through blocks 256, 258, and 260 performing the test of the relay under test 24. At block 262 the relay test device 10 analyzes the final state of the relay under test 24 to determine whether the relay under test 24 passed or failed the test. The method proceeds to block 264 where the relay test device 10 writes the initial settings to the relay under test 24, to restore the relay under test 24 to its initial condition. The method proceeds to block 264 where the relay test device 10 reports the test result to the user interface 20.

Turning now to FIG. 6, another method for using the relay test device 10 is depicted. The method depicted in FIG. 6 is substantially the same as the method depicted in FIG. 5 with differences noted below. It is understood that after block 300 and before block 302 a field operator without special knowledge of relays or electrical power distribution technology or regulations may transport the relay test device 10 to the field, connect the relay test device 10 to the relay under test 24, and initiate the test procedure. After testing the relay under test 24 according to a first group of relay settings, the method proceeds to block 312 where the relay test device 10 analyzes the state of the relay under test 24 to determine whether the relay under test 24 passed or failed the test according to the particular group of relay settings. The method proceeds to block 314 where the method returns to block 304 if the relay under test 24 has not been tested according to all groups of relay settings which the test procedure calls for testing. By looping through blocks 304, 306, 308, 310, and 312 the relay under test 24 is tested according to each of several test relay settings. At block 314 if the test of the relay under test 24 is complete, the method proceeds to block 316 where the relay test device 10 writes the initial relay settings to the relay under test 24, to restore the relay under test 24 to its initial condition. The method proceeds to block 318 where the relay test device 10 reports the test results to the UI 20.

Turning now to FIG. 7a, another method for using the relay test device 10 is depicted. The method depicted in FIG. 7a is substantially the same as the method depicted in FIG. 4 with differences noted below. It is understood that after block 324 and before block 326 a field operator without special knowledge of relays or electrical power distribution technology or regulations may transport the relay test device 10 to the field, connect the relay test device 10 to the relay under test 24, and initiate the test procedure. At block 326 the relay test device 10 reads the as found relay settings. The method proceeds to block 328 where the test relay device 10 performs an action of the test procedure based on the as found relay settings which were read in. This step corresponds to testing the relay under test 24 according to its as found settings, and if a relay having different settings from another relay is tested using the same test procedure stored in the relay test device 10, the test actions will differ accordingly. The method proceeds to block 330 where the relay test device 10 monitors the relay under test 24. The method proceeds to block 332 where the method returns to block 328 if the test of the relay under test 24 is incomplete. When the test of the relay under test 24 is complete, the method proceeds to block 334 where the relay test device 10 analyzes the final state of the relay under test 24 to determine whether the relay under test 24 passed or failed the test. The method then proceeds to block 336 where the relay test device 10 reports the test result to the UI 20.

Turning now to FIG. 7b, another method for using the relay test device 10 is depicted. The method depicted in FIG. 7b is substantially the same as the method depicted in FIG. 4 with differences noted below. It is understood that after block 354 and before block 356 a field operator without special knowledge of relays or electrical power distribution technology or regulations may transport the relay test device 10 to the field, connect the relay test device 10 to the relay under test 24, and initiate the test procedure. At block 354 the procedure step contains both a test procedure and a new desired characteristic behavior of the relay under test 24 based on settings to be determined by test. At block 356 the relay test device 10 reads the initial relay settings.

The method proceeds to block 358 where the test relay device 10 performs an action of the test procedure based on the as found relay settings which were read in. The method proceeds to block 360 where if the relay under test 24 passes the test with expected results, the relay can then be re-programmed with new settings which may cause the relay under test 24 to exhibit the desired characteristic stored in block 354. Assuming the results of the testing at block 358 were successful, the method proceeds to block 362.

In block 362 a search algorithm determines relay settings that may lead the relay under test 24 to exhibit the desired characteristic when tested. The search algorithm may be designed to approach the settings that produce the desired characteristic by determining a succession of maximum and minimum settings and refining the maximum and minimum settings each iteration through the test loop. Alternately, another algorithm for finding relay settings suitable for testing the relay under test 24 may be employed. The relay under test 24 is reprogrammed with the determined relay settings utilizing Ethernet, RS-232 or other communications means used by industry standard relays.

The method proceeds to block 364 where the relay under test 24 is tested according to the settings. The method proceeds to block 366 where if the relay under test 24 exhibited the desired characteristic the test is successful and the method exits. If the relay under test 24 did not exhibit the desired characteristic, the method proceeds to block 368. In block 368 if the characteristic is determined to be unachievable, for example if a maximum number of test iterations have completed without achieving the desired characteristic, the method exits otherwise the method returns to block 362. By looping through blocks 362, 364, 366, and 368 the relay under test 24 is tested according to a number of settings to find if the desired characteristic can be achieved.

The settings required and actual characteristics of the relay under test 24 are logged into memory or sent via network communications to a data storage system, such as a PC or web server for analysis by personnel skilled in the art of protective relay settings, application and testing.

The relay test device 10 provides a stand-alone test set which may be used by personnel with relatively limited knowledge and experience of relays and electrical power distribution. The relay test device 10 may simplify the complex field test procedures associated with other test devices down to procedures involving pointing and clicking by field service personnel which causes complete tests to run and test results to be reported. In an embodiment, the relay test device 10 may support initiating tests from and displaying and analyzing results on a general purpose computer system, such as a personal computer or a workstation, for example in a manufacturer's relay test shop. In another embodiment the relay test device 10 may utilize network communications, such as Ethernet, Internet, intranet or wireless networks, to support initiating tests from and displaying results on a general purpose computer system, such as a personal computer or workstation while the relay test device 10 is located remotely from the general purpose computer system, such as relay test device 10 located at an electrical distribution substation hundreds or thousands of miles away from the general purpose personal computer located at a main service office where skilled personnel may be consolidated to reduce costs, utilizing less expensive field personnel for traveling from site to site and connecting relay test device 10 to relays under test 24. Software loaded on a personal computer, workstation, or the relay test device 10 may be used to create, analyze, and perform relay tests.

Software and Firmware Installation System for a Relay Test Device

Installing versions of software and firmware into the relay test device 10 may involve changing the stored instructions associated with DSPs, PLDs, ASICs, uPs, and uCs inside the relay test device 10 and in the UI 20. The versions of software and firmware may be updates, functional corrections, revisions, prior versions, and/or new versions. The versions of software may include test procedures. All of these software and firmware changes or installations are contemplated by the use of the term version or installation. Installing versions of software and firmware may entail installing the versions into memory in a specific order. In one embodiment, the relay test device 10 may initiate contact with a remote computer system in the event of a failure or for upgrading or updating. Communication could also be initiated by the remote computer system, such as a support computer maintained by the device vendor. Either or both the remote computer system or relay test device 10 may perform a diagnostic analysis of the relay test device 10 to determine the vers