Thin film magnetic memory device having redundant configuration Number:7,110,288 from the United States Patent and Trademark Office (PTO) owispatent Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.<H configuration, redundant, Thin, film, magne, 7110288.html, Patent, pto, 7110288

Title: Thin film magnetic memory device having redundant configuration

Abstract: Normal memory cells are arranged in rows and columns, and dummy memory cells are arranged to form dummy memory cell rows by sharing memory cell columns with the normal memory cells. When there is at least one defect in the normal memory cells and/or the dummy memory cells, replacement/repair is carried out using a redundant column in a unit of memory cell column. The redundant column includes not only spare memory cells for repair of the normal memory cells but also spare dummy memory cells for repair of the dummy memory cells.

Patent Number: 7,110,288 Issued on 09/19/2006 to Hidaka

Inventors: Hidaka; Hideto (Hyogo, JP)
Assignee: Renesas Technology Corp. (Tokyo, JP)

Appl. No.: 11/038,064

Filed: January 21, 2005

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10316082	Dec., 2002	6876576

Foreign Application Priority Data


Jun 04, 2002 [JP]			2002-163135

Current U.S. Class: 365/171 ; 365/158; 365/200; 365/210; 365/225.5; 365/66

Current International Class: G11C 11/14 (20060101); G11C 11/00 (20060101); G11C 29/00 (20060101); G11C 7/02 (20060101)

Field of Search: 365/158,171,173,200,209,210

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2001-284456	Oct., 2001	JP
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Other References

"A 10ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in Each Cell", Scheuerlein et al., ISSCC Digest of Technical Papers, TA 7.2, Feb. 2000, pp. 94-95, 128-129, 409-410. cite- d by other .
"Nonvolatile RAM based on Magnetic Tunnel Junction Elements", Durlam et al., ISSCC Digest of Technical Papers, TA 7.3, Feb. 2000, pp. 96-97, 130-131, 410-411. cited by other .
"A 256kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM", Naji et al., ISSCC Digest of Technical Papers, TA7.6, Feb. 2001, pp. 94-95, 122-123, 404-405, 438. cited by other .
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Primary Examiner: Zarabian; Amir
Assistant Examiner: Pham; Ly Duy
Attorney, Agent or Firm: McDermott Will & Emery LLP

Parent Case Text

This application is a divisional of application Ser. No. 10/316,082 filed Dec. 11, 2002 now U.S. Pat. No. 6,876,576.

Claims

What is claimed is:

1. A thin film magnetic memory device, comprising: a matrix including: a plurality of memory cells aligned in a first direction, each memory cell having an electric resistance in accordance with magnetically written data; a plurality of dummy memory cells aligned in the first direction, each having a prescribed electric resistance; a plurality of redundant memory cells aligned in a second direction, including a first spare memory cell for replacement of any of the memory cells, and a second spare memory cell for replacement of any of the dummy memory cells; and a data read circuit performing data read based on an electric resistance difference between selected one of said plurality of memory cells and one of said plurality of dummy memory cells, wherein the plurality of memory cells and the first spare memory cell form a row or a column of the matrix, the plurality of dummy memory cells and the second spare memory cell form another row or column of the matrix, said plurality of dummy memory cells are arranged to form at least one row, and said plurality of dummy memory cells are selectively connected to said data read circuit based on a result of column selection.

2. A thin film magnetic memory device, comprising: a matrix including: a plurality of memory cells aligned in a first direction, each memory cell having an electric resistance in accordance with magnetically written data; a plurality of dummy memory cells aligned in the first direction, each having a prescribed electric resistance; a plurality of redundant memory cells aligned in a second direction, including a first spare memory cell for replacement of any of the memory cells, and a second spare memory cell for replacement of any of the dummy memory cells; and a data read circuit performing data read based on an electric resistance difference between selected one of said plurality of memory cells and one of said plurality of dummy memory cells, wherein the plurality of memory cells and the first spare memory cell form a row or a column of the matrix, the plurality of dummy memory cells and the second spare memory cell form another row or column of the matrix, said plurality of dummy memory cells are arranged to form at least one column, and said plurality of dummy memory cells are selectively connected to said data read circuit based on a result of row selection.

3. A thin film magnetic memory device, comprising: a matrix including a plurality of memory cells aligned in a first direction, each memory cell having an electric resistance in accordance with magnetically written data, a plurality of dummy memory cells aligned in the first direction, each having a prescribed electric resistance, a plurality of redundant memory cells aligned in a second direction, including a first spare memory cell for replacement of any of the memory cells, and a second spare memory cell for replacement of any of the dummy memory cells; and a data read circuit performing data read based on an electric resistance difference between selected one of said plurality of memory cells and one of said plurality of dummy memory cells, wherein the plurality of memory cells and the first spare memory cell form a first row of the matrix, the plurality of dummy memory cells and the second spare memory cell form a second row of the matrix, the matrix includes a plurality of the first rows and at least one second row, the thin film magnetic memory device further comprising: a plurality of first signal lines provided corresponding to the first rows each including the memory cells and the first spare memory cell, and used for selection of said first rows; and at least one second signal line provided corresponding to the at least one second row and used for selection of said at least one second row; the row selection for the first spare memory cells in the respective first rows being conducted via said plurality of first signal lines, and the row selection for the second spare memory cell in the at least one second row being conducted via said at least one second signal line.

4. A thin film magnetic memory device, comprising: a matrix including a plurality of memory cells aligned in a first direction, each memory cell having an electric resistance in accordance with magnetically written data, a plurality of dummy memory cells aligned in the first direction, each having a prescribed electric resistance, a plurality of redundant memory cells aligned in a second direction, including a first spare memory cell for replacement of any of the memory cells, and a second spare memory cell for replacement of any of the dummy memory cells; and a data read circuit performing data read based on an electric resistance difference between selected one of said plurality of memory cells and one of said plurality of dummy memory cells, wherein the plurality of memory cells and the first spare memory cell form a first column of the matrix, the plurality of dummy memory cells and the second spare memory cell form a second column of the matrix, the matrix includes a plurality of the first columns and at least one second column, the thin film magnetic memory device further comprising: a plurality of bit lines provided corresponding to the first columns each including the memory cells and the first spare memory cell; and a dummy bit line provided corresponding to the second column of said plurality of dummy memory cells and the second spare memory cell; in each first column, corresponding memory cells and corresponding first spare memory cell being connected to corresponding one of said plurality of bit lines, and in the second column, said plurality of dummy memory cells and said second spare memory cell being connected to said dummy bit line.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to thin film magnetic memory devices, and more particularly to a thin film magnetic memory device provided with a redundant configuration.

2. Description of the Background Art

A magnetic random access memory (MRAM) device has attracted attention as a memory device capable of non-volatile data storage with low power consumption. The MRAM device stores data in a non-volatile manner using a plurality of thin film magnetic elements formed in a semiconductor integrated circuit, and permits random access to the respective thin film magnetic element.

In particular, it has recently been reported that provision of thin film magnetic elements having magnetic tunnel junctions (MTJ) as memory cells significantly improves the performance of the MRAM device. The MRAM device provided with such memory cells having magnetic tunnel junctions is disclosed in technical documents such as "A 10 ns Read and Write Non-Volatile Memory Array Using a Magnetic Tunnel Junction and FET Switch in each Cell", ISSCC Digest of Technical Papers, TA7.2, February 2000, "Nonvolatile RAM based on Magnetic Tunnel Junction Elements", ISSCC Digest of Technical Papers, TA7.3, February 2000, and "A 256 kb 3.0V 1T1MTJ Nonvolatile Magnetoresistive RAM", ISSCC Digest of Technical Papers, TA7.6, February 2001.

FIG. 17 is a schematic diagram showing a configuration of a memory cell having a magnetic tunnel junction (hereinafter, also simply referred to as the "MTJ memory cell").

Referring to FIG. 17, the MTJ memory cell includes a tunneling magneto-resistance element TMR having its electric resistance changing according to a level of stored data, and an access element ATR for forming a path of a sense current Is passing through tunneling magneto-resistance element TMR at the time of data read. Hereinafter, access element ATR is also referred to as an access transistor ATR, since it is typically formed of a field effect transistor. Access transistor ATR is coupled between tunneling magneto-resistance element TMR and a fixed voltage (ground voltage Vss).

A write word line WWL for designating data write, a read word line RWL for executing data read, and a bit line BL as a data line for transmitting an electric signal corresponding to a level of stored data at the time of the data read and the data write, are arranged for the MTJ memory cell.

FIG. 18 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.

Referring to FIG. 18, tunneling magneto-resistance element TMR has a ferromagnetic layer (hereinafter, also simply referred to as the "fixed magnetic layer") FL having a fixed, constant direction of magnetization, and a ferromagnetic layer (hereinafter, also simply referred to as the "free magnetic layer") VL magnetized in a direction corresponding to the magnetic field externally applied. A tunneling barrier (tunneling film) TB formed of an insulating film is provided between fixed magnetic layer FL and free magnetic layer VL. Free magnetic layer VL is magnetized in a direction the same as or opposite to fixed magnetic layer FL in accordance with the level of the stored data to be written. Fixed magnetic layer FL, tunneling barrier TB and free magnetic layer VL form a magnetic tunnel junction.

At the time of data read, access transistor ATR turns on in response to activation of read word line RWL. This allows a sense current Is to flow through a current path from bit line BL via tunneling magneto-resistance element TMR and access transistor ATR to ground voltage Vss.

The electric resistance of tunneling magneto-resistance element TMR changes in accordance with the relative relation between the magnetization directions of fixed magnetic layer FL and free magnetic layer VL. Specifically, when the magnetization direction of fixed magnetic layer FL and the magnetization direction of free magnetic layer VL are the same (parallel), the electric resistance of tunneling magneto-resistance element TMR becomes small compared to the case where the two layers have opposite (anti-parallel) magnetization directions.

Thus, when free magnetic layer VL is magnetized in a direction according to the stored data, voltage change occurring in tunneling magneto-resistance element TMR due to sense current Is will differ in accordance with the level of the stored data. Accordingly, if sense current Is is passed through tunneling magneto-resistance element TMR after precharging of bit line BL to a certain voltage, for example, then the stored data in a MTJ memory cell can be read by sensing the voltage of bit line BL.

FIG. 19 is a conceptual diagram illustrating a data write operation to the MTJ memory cell.

Referring to FIG. 19, at the time of data write, read word line RWL is inactivated, and access transistor ATR is turned off. In this state, a data write current for magnetizing free magnetic layer VL to a direction in accordance with the write data is passed through write word line WWL and through bit line BL. The magnetization direction of free magnetic layer VL is determined by the data write currents flowing through the respective lines of write word line WWL and bit line BL.

FIG. 20 is a conceptual diagram illustrating a relation between the data write current at the time of data write to the MTJ memory cell and the magnetization direction of the tunneling magneto-resistance element.

Referring to FIG. 20, the horizontal axis H (EA) represents the magnetic field applied to free magnetic layer VL within tunneling magneto-resistance element TMR in an easy-to-magnetize, or, easy axis (EA) direction. The vertical axis H (HA) represents the magnetic field acting on free magnetic layer VL in a hard-to-magnetize, or, hard axis (HA) direction. Magnetic fields H (EA) and H (HA) correspond respectively to two magnetic fields generated by the currents flowing through bit line BL and write word line WWL.

In the MTJ memory cell, the fixed magnetization direction of fixed magnetic layer FL is along the easy axis of free magnetic layer VL. Free magnetic layer VL is magnetized in the parallel (same) or anti-parallel (opposite) direction with respect to fixed magnetic layer FL along the easy axis direction, in accordance with the level ("1" or "0") of the stored data. Hereinafter, the electric resistances of tunneling magneto-resistance element TMR corresponding to the two magnetization directions of free magnetic layer VL will be referred to as R1 and R0 (R1>R0). The MTJ memory cell can store data of one bit ("1" or "0") corresponding to respective one of the two magnetization directions of free magnetic layer VL.

The magnetization direction of free magnetic layer VL can be rewritten only in the case where the sum of applied magnetic fields H (EA) and H (HA) reaches a region outside the asteroid characteristic line shown in FIG. 20. In other words, the magnetization direction of free magnetic layer VL would not change if the applied data write magnetic field has an intensity corresponding to the region inside the asteroid characteristic line.

As seen from the asteroid characteristic line, a magnetization threshold value necessary to change the magnetization direction along the easy axis can be lowered by applying to free magnetic layer VL the magnetic field in the hard axis direction.

Assume that operating points at the time of data write are designed as in the example shown in FIG. 20. In this case, in the MTJ memory cell to which data is to be written, the data write magnetic field in the easy axis direction is designed to have an intensity of H.sub.WR. In other words, the value of the data write current to be passed through bit line BL or write word line WWL is designed such that the relevant data write magnetic field H.sub.WR is obtained. In general, data write magnetic field H.sub.WR is expressed by the sum of a switching magnetic field H.sub.SW necessary to switch the magnetization direction and a margin .DELTA.H: H.sub.WR=H.sub.SW+.DELTA.H.

To rewrite the stored data of the MTJ memory cell, or, the magnetization direction of tunneling magneto-resistance element TMR, a data write current of at least a prescribed level should be passed through both write word line WWL and bit line BL. By doing so, free magnetic layer VL in tunneling magneto-resistance element TMR can be magnetized in the same (parallel) or opposite (anti-parallel) direction with respect to fixed magnetic layer FL, in accordance with the direction of the data write magnetic field along the easy axis (EA). The magnetization direction once written into tunneling magneto-resistance element, i.e., the stored data of the MTJ memory cell, is held in a non-volatile manner until new data is written.

As such, the electric resistance of tunneling magneto-resistance element TMR changes according to the magnetization direction that is rewritable with the data write magnetic field being applied. Thus, by making the two magnetization directions of free magnetic layer VL in tunneling magneto-resistance element TMR correspond to the levels ("1" and "0") of the stored data, the data can be stored in a non-volatile manner.

In the MRAM device, data is read utilizing an electric resistance difference .DELTA.R=(Rmax-Rmin) that is a junction resistance difference in tunneling magneto-resistance element TMR corresponding to the difference of the stored data levels. In other words, data read is performed by sensing a current passing through a selected memory cell, i.e., sense current Is.

Generally, in addition to the normal MTJ memory cells for use in data storage, dummy memory cells are provided for comparison with the selected memory cell. The dummy memory cells need to be fabricated such that they each have an electric resistance of an intermediate level between the two electric resistances Rmax and Rmin corresponding to the stored data levels of the MTJ memory cell. Implementation of such an electric resistance requires special design and fabrication of the dummy memory cells. If the dummy memory cells do not have electric resistance values as designed, data read margin would be impaired.

Further, generally in a memory device, in addition to provision of a plurality of normal memory cells being selected with address signals, a redundant configuration for repair of defects in the normal memory cells is provided to improve manufacturing yield. In the redundant configuration, replacement/repair of the defective memory cells is conducted in units of sections, using spare memory cells additionally provided.

In the redundant configuration in the MRAM device, it is necessary to make it possible to replace/repair not only the normal MTJ memory cells but also the dummy memory cells. In other words, the spare memory cells should be arranged efficiently, taking account of replacement of the dummy memory cells as well as the normal memory cells.

SUMMARY OF THE INVENTION

An object of the present invention is to provide a thin film magnetic memory device provided with a redundant configuration permitting efficient replacement/repair of both normal MTJ memory cells provided for data storage and dummy memory cells provided for comparison with the normal MTJ memory cells at the time of data read.

In brief, the present invention is a thin film magnetic memory device including a plurality of memory cells, a plurality of dummy memory cells, a data read circuit, and a redundant unit. The plurality of memory cells are arranged in rows and columns, and each memory cell has an electric resistance in accordance with magnetically written data. The plurality of dummy memory cells each have a prescribed electric resistance, and are arranged such that they share one of the rows and columns with the plurality of memory cells and form the other of the rows and columns. The data read circuit performs data read based on an electric resistance difference between selected one of the plurality of memory cells and one of the plurality of dummy memory cells. The redundant unit is for replacing a defective memory cell included in the plurality of memory cells and the plurality of dummy memory cells in a unit of the one of the row and column. The redundant unit includes a plurality of first spare memory cells and at least one second spare memory cell arranged to form the one of the row and column. The plurality of first spare memory cells are arranged such that they share the other of the rows and columns with the plurality of memory cells for replacement of the defective memory cell included in the plurality of memory cells. The second spare memory cell is arranged such that it shares the other of the row and column with the plurality of dummy memory cells for replacement of the defective memory cell included in the plurality of dummy memory cells.

Accordingly, the main advantage of the present invention is that defects in not only the normal memory cells but also the dummy memory cells can be replaced/repaired in a unit of memory cell column by the redundant unit including both the first and second spare memory cells, since the dummy memory cells are arranged in a direction that is different from the direction in which the first and second spare memory cells are arranged. That is, it is possible to reduce the layout area of the first and second spare memory cells and to downsize the memory array.

According to another aspect of the present invention, the thin film magnetic memory device includes a plurality of memory cells, a plurality of dummy memory cells, a resistance adjusting portion, a data read circuit, and a redundant unit. The memory cells are arranged in rows and columns, and each memory cell has an electric resistance in accordance with magnetically written data. The dummy memory cells each have the same electric resistance characteristic as each memory cell, and data of a prescribed level is written in advance therein. The dummy memory cells each share one of the row and column with the memory cells, and form the other of the row and column. The resistance adjusting portion electrically couples a prescribed electric resistance to at least one of the memory cell and the dummy memory cell. The data read circuit performs data read based on a difference between combined resistance of selected one of the plurality of memory cells and the resistance adjusting portion and combined resistance of one of the plurality of dummy memory cells and the resistance adjusting portion. The redundant unit is for replacement of a defective memory cell included in the memory cells and the dummy memory cells in a unit of the other of the row and column. The redundant unit includes a plurality of spare memory cells arranged in the other of the row and column such that they share the one of the rows and columns with the memory cells and the dummy memory cells. Each spare memory cell has the same electric resistance characteristic as each memory cell.

In the memory array configuration having dummy memory cells of the same configurations as memory cells arranged therein, the thin film magnetic memory device of the present aspect permits replacement/repair of both the defective memory cells and the defective dummy memory cells in a unit of row or column, using a single redundant unit formed of the spare memory cells. Further, since the dummy memory cells each have the same configuration and shape as the memory cell, special design or manufacturing steps are unnecessary for fabrication of the dummy memory cells. Therefore, an increase of chip area due to complication of the structure, degradation of process margin of the memory array and other problems are prevented.

According to a further aspect of the present invention, the thin film magnetic memory device permitting parallel input/output of data of m bits (m is an integer not less than 2) includes a plurality of blocks, m data terminals, and a shift redundancy circuit. Each of the plurality of blocks includes a plurality of memory cells arranged in rows and columns, and a plurality of dummy memory cells arranged such that they share the columns with the plurality of memory cells and form dummy memory cell rows. Each memory cell has an electric resistance in accordance with magnetically written data. Each dummy memory cell has a prescribed electric resistance. Each block further includes (m+1) memory cell columns formed of the memory cells and the dummy memory cells, and (m+1) data line pairs each formed of complementary first and second data lines and provided corresponding to the (m+1) memory cell columns. Each of the first and second data lines is connected to one and the other of one memory cell and one dummy memory cell belonging to corresponding one of the (m+1) memory cell columns at the time of data read from corresponding one of the plurality of blocks. The m data terminals are provided for sending data to and receiving data from the outside. The shift redundancy circuit is provided, when there is a defect in at least one of the memory cells and the dummy memory cells in a selected block, for reading and writing the data sent/received by the m data terminals using the m data line pairs other than the data line pair connected to the defect in the selected block.

The relevant thin film magnetic memory device can replace/repair defects in both the memory cells and the dummy memory cells in a unit of memory cell column, for each block readable/writable data of multiple bits in parallel, by performing shift redundancy using the memory cell columns including the one additionally provided. Accordingly, the redundant configuration becomes more efficient in the memory array configuration where multiple bits are input/output in parallel.

According to yet another aspect of the present invention, the thin film magnetic memory device includes a plurality of memory cells, a plurality of dummy memory cells, first and second data lines, a data read circuit, and a dummy reference potential generating portion. The memory cells each have an electric resistance in accordance with magnetically written data. The dummy memory cells each have a prescribed electric resistance. The first and second data lines are supplied with prescribed data read currents, and are connected respectively to one and the other of one of the plurality of memory cells and one of the plurality of dummy memory cells in a normal data read operation. The data read circuit performs data read based on a voltage difference between the first and second data lines. When one of the first and second data lines is connected to one of the plurality of dummy memory cells in a test operation, the dummy reference potential generating portion is connected to the other of the first and second data lines instead of one of the plurality of memory cells. The dummy reference potential generating portion applies to the other of the first and second data lines a potential that is different from a potential of the one of the first and second data lines to which the prescribed electric resistance is connected.

In the relevant thin film magnetic memory device, the data read circuit used in the normal operation can also be used in the test operation to detect defects in the dummy memory cells.

The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram showing the entire configuration of an MRAM device according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration of the memory array according to the first embodiment.

FIG. 3 is a block diagram showing a configuration of the redundancy control circuit shown in FIG. 1.

FIG. 4 shows operating waveforms in the data read operation and data write operation to illustrate replacement/repair in the MRAM device.

FIGS. 5 7 are circuit diagrams showing configurations of the memory arrays according to the first through third modifications of the first embodiment.

FIG. 8 is a circuit diagram showing a memory array configuration and a configuration for reading data from the memory array according to a second embodiment of the present invention.

FIG. 9 is a circuit diagram showing a configuration of the redundancy control circuit according to the second embodiment.

FIGS. 10 and 11 are circuit diagrams showing memory array configurations and configurations for reading data from the memory arrays according to first and second modifications, respectively, of the second embodiment.

FIGS. 12 and 13 are circuit diagrams showing memory array configurations according to third and fourth embodiments, respectively, of the present invention.

FIG. 14 is a circuit diagram showing a memory array configuration and a configuration for reading data from and writing data to the memory array according to a fifth embodiment of the present invention.

FIG. 15 is a block diagram showing a configuration of the redundancy control circuit shown in FIG. 14.

FIG. 16 is a circuit diagram showing a test circuit of dummy memory cells according to a sixth embodiment of the present invention.

FIG. 17 is a schematic diagram showing a configuration of an MTJ memory cell.

FIG. 18 is a conceptual diagram illustrating a data read operation from the MTJ memory cell.

FIG. 19 is a conceptual diagram illustrating a data write operation to the MTJ memory cell.

FIG. 20 is a conceptual diagram illustrating a relation between a data write current at the time of data write to the MTJ memory cell and a magnetization direction of the tunneling magneto-resistance element.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First Embodiment

Referring to FIG. 1, the MRAM device 1 according to the first embodiment of the present invention performs random access in accordance with externally applied control signal CMD and address signal ADD, and performs input of write data DIN and output of read data DOUT. The data read operation and the data write operation in MRAM device 1 are performed at timings in synchronization with an externally applied clock signal CLK, for example. Alternatively, the operating timings may be determined within the device, unprovided with external clock signal CLK.

MRAM device 1 includes: an address terminal 2 receiving input of address signal ADD; a control signal terminal 3 receiving input of control signal CMD and clock signal CLK; a signal terminal 4a receiving input of a program signal PRG that is activated in a program operation; a control circuit 5 for controlling the entire operations of MRAM device 1 in response to control signal CMD and clock signal CLK; and a memory array 10 having a plurality of MTJ memory cells arranged in rows and columns.

Memory array 10, whose configuration will be described later in detail, includes: a plurality of normal MTJ memory cells (hereinafter, also simply referred to as "normal memory cells") arranged in rows and columns that are selectable by address signal ADD; a plurality of dummy memory cells provided for comparison with the normal memory cell selected as an access target (hereinafter, also referred to as the "selected memory cell") in a data read operation; and a redundant circuit (not shown) for replacing/repairing the normal memory cell(s) and/or the dummy memory cell(s) suffering defect(s) (hereinafter, also commonly referred to as the "defective memory cell(s)") in a unit of prescribed redundancy repair section. Generally, the unit of redundancy repair section is a row, a column, or a data I/O line, in which case, the redundant circuit corresponds to a redundant row, a redundant column, or a redundant block corresponding to a spare I/O line, respectively.

The dummy memory cells are arranged to share one of the rows and columns with the normal memory cells. Hereinafter, both the row formed only of the normal memory cells and the row shared by the normal and dummy memory cells are generally called the "memory cell rows". Similarly, both the column formed only of the normal memory cells and the column shared by the normal and dummy memory cells are generally called the "memory cell columns".

A plurality of write word lines WWL and read word lines RWL are arranged corresponding to the respective memory cell rows. Complementary bit lines BL and /BL constituting bit line pairs are arranged corresponding to the respective memory cell columns.

MRAM device 1 further includes a row decoder 20, a column decoder 25, a word line driver 30, and read/write control circuits 50, 60.

Row decoder 20 performs row selection in memory array 10 in accordance with a row address RA indicated by address signal ADD. Column decoder 25 performs column selection in memory array 10 in accordance with a column address CA indicated by address signal ADD. Word line driver 30 selectively activates read word line RWL or write word line WWL based on the row selection result of row decoder 20. Row address RA and column address CA indicate a selected memory cell that is selected as a target of data read or data write.

Write word line WWL is coupled to a ground voltage Vss in a region 40 on the other side of memory array 10 from a region where word line driver 30 is arranged. Read/write control circuits 50, 60 collectively represent circuit groups arranged adjacent to memory array 10 for making a data write current and a sense current (data read current) pass through bit lines BL and /BL of a memory cell column corresponding to the selected memory cell (hereinafter, also referred to as the "selected column").

MRAM device 1 further includes a program circuit 100 and a redundancy control circuit 105. Program circuit 100 holds, in a non-volatile manner, defective addresses for specifying defective memory cells as program information. The defective addresses correspond to the row addresses indicating memory cell rows having the defective memory cells therein (hereinafter, also referred to as the "defective rows") and/or the column addresses indicating memory cell columns having the defective memory cells therein (hereinafter, also referred to as the "defective columns").

These defective addresses are read out based on a designation from control circuit 5 and transmitted to redundancy control circuit 105, in the data write and read operations where accesses should be made based on address signal ADD. Redundancy control circuit 105 performs matching/comparison between the defective addresses transmitted from program circuit 100 and address signal ADD input to the address terminal. Alternatively, the functions of program circuit 100 and redundancy control circuit 105 may be incorporated in row decoder 20 or column decoder 25.

Hereinafter, a configuration for redundancy repair according to the first embodiment is described wherein a redundant column is used for replacement in a unit of memory cell column.

Referring to FIG. 2, memory array 10 includes a plurality of memory cells MC arranged in rows and columns, a plurality of dummy memory cells DMC, and a redundant column 11C. The configuration of each normal memory cell MC is the same as described in conjunction with FIG. 17, and its electric resistance is set to either Rmax or Rmin in accordance with the magnetically written data.

Dummy memory cells DMC are arranged in the row direction such that they share memory cell columns with normal memory cells MC and form two dummy memory cell rows. Each dummy memory cell DMC has a dummy resistance element TMRd and a dummy access transistor ATRd. Dummy memory cell DMC has a prescribed electric resistance when selected, i.e., when its dummy access transistor ATRd is on. Specifically, the electric resistance of the dummy memory cell when selected is set to an intermediate level of two kinds of electric resistances Rmax and Rmin of the normal memory cell, preferably to Rmin+.DELTA.R/2.

To achieve dummy memory cell DMC having such characteristics, for example, dummy resistance element TMRd is first designed the same as tunneling magneto-resistance element TMR of normal memory cell MC, and stored data corresponding to electric resistance Rmin is prewritten therein. The transistor size of dummy access transistor ATRd is then differentiated from that of access transistor ATR, or the electric resistance of dummy resistance element TMRd is set to a specific value. Data write in a normal operation is not performed on dummy memory cell DMC, since its electric resistance should be maintained at a prescribed value.

Redundant column 11C has spare memory cells SMC and spare dummy memory cells SDMC arranged in the column direction. Spare memory cells SMC each have the configuration and characteristics the same as those of normal memory cell MC, and are arranged to share memory cell rows with normal memory cells MC. Spare dummy memory cells SDMC, each having the same configuration and characteristics as dummy memory cell DMC, are arranged to share dummy memory cell rows with dummy memory cells DMC.

In memory array 10, read word lines RWL and write word lines WWL are arranged corresponding to a plurality of memory cell rows shared by normal memory cells MC and spare memory cells SMC. Dummy read word lines DRWL0 and DRWL1 are provided corresponding to the two dummy memory cell rows shared by dummy memory cells DMC and spare dummy memory cells SDMC. Thus, normal memory cells MC and spare memory cell SMC belonging to the same memory cell row are selected by common read word line RWL (in the data read operation) and common write word line WWL (in the data write operation), and dummy memory cells DMC and spare dummy memory cell SDMC belonging to the same dummy memory cell row are selected by common dummy read word line DRWL0 or DRWL1 in the data read operation.

Further, complementary bit lines BL and /BL are arranged corresponding to each of m memory cell columns (m is a natural number) shared by normal memory cells MC and dummy memory cells DMC. Complementary spare bit lines SBL and /SBL are provided corresponding to redundant column 11C.

Hereinafter, write word lines, read word lines and bit lines will be collectively represented as WWL, RWL and BL (/BL), while specific write word lines, read word lines and bit lines will be represented as WWL1, RWL1 and BL1 (/BL1), for example, with accompanying numerals. The high voltage state (power supply voltages Vcc1, Vcc2) and low voltage state (ground voltage Vss) of signals and signal lines will also be simply referred to as an "H level" and an "L level", respectively.

Normal memory cells MC in every other row are connected to either one of bit lines BL and /BL. For example, focusing on the normal memory cells belonging to the first memory cell column, the normal memory cell in the first row is coupled to bit line BL1, and the normal memory cell in the second row is coupled to bit line /BL1. Likewise, the normal memory cells and spare memory cells in the odd rows are connected to bit lines BL1 BLm, and those in the even rows are connected to the other bit lines /BL1 /BLm.

Dummy memory cells DMC are arranged in two rows x m columns, the two rows corresponding to dummy read word lines DRWL0 and DRWL1. The dummy memory cells selected by dummy read word line DRWL0 are coupled to respective bit lines BL1 BLm. The remaining dummy memory cells selected by dummy read word line DRWL1 are coupled respectively to bit lines /BL1 /BLm.

As in normal memory cells MC, spare memory cells SMC in odd rows are connected to spare bit line SBL, and those in even rows are connected to spare bit line /SBL. Likewise, spare dummy memory cells SDMC selected by respective dummy read word lines DRWL0 and DRWL1 are connected to spare bit lines SBL and /SBL, respectively.

Although read word lines RWL1, RWL2, write word lines WWL1, WWL2, bit lines BL1, /BL1, BLm /BLm corresponding to the first and m-th memory cell columns and the first and second memory cell rows have been shown representatively in FIG. 2, the similar configurations are provided for the remaining memory cell columns and memory cell rows.

In the data read operation, word line driver 30 selectively activates read word lines RWL and dummy read word lines DRWL0, DRWL1 to an H level (of power supply voltage Vcc1) in accordance with the row selection result. Specifically, when an odd row is selected and normal memory cells MC and spare memory cell SMC in the selected row are connected to bit lines BL1 BLm and spare bit line SBL, then dummy read word line DRWL1 is also activated, and corresponding dummy memory cells DMC and spare dummy memory cell SDMC are connected to bit lines /BL1 /BLm and spare bit line /SBL. By comparison, when an even row is selected, dummy read word line DRWL0 is activated in addition to the read word line of the selected row.

In the data write operation, word line driver 30 couples an end of write word line WWL of the selected row to power supply voltage Vcc2. This permits a data write current Ip to flow on write word line WWL of the selected row in the row direction from word line driver 30 toward region 40. The write word lines of non-selected rows are coupled to ground voltage Vss by word line driver 30.

Column select lines CSL1 CSLm for performing column selection are provided corresponding to respective memory cell columns. A spare column select line SCSL is also arranged corresponding to redundant column 11C. Column decoder 25 selectively activates (to an H level) one of column select lines CSL1 CSLm and spare column select line SCSL at each time of data write and data read in accordance with a decoded result of column address CA, i.e., the column selection result. The column selection will be described later in detail.

Further, complementary data buses DB and /DB are arranged in a peripheral portion of memory array 10. Read/write control circuit 50 shown in FIG. 1 includes: a data write circuit 51W, a data read circuit 51R, column select gates CSG1 CSGm provided corresponding to respective memory cell columns, and a spare column select gate SCSG provided corresponding to redundant column 11C. Hereinafter, column select lines CSL1 CSLm and column select gates CSG1 CSGm are also simply referred to as column select line CSL and column select gate CSG collectively.

Each column select gate CSG has a transistor switch electrically coupled between data bus DB and corresponding bit line BL, and a transistor switch electrically coupled between data bus /DB and corresponding bit line /BL. The transistor switches turn on/off in accordance with a voltage of corresponding column select line CSL. That is, each column select gate CSG, when corresponding column select line CSL is activated to a selected state (of an H level), electrically couples data buses DB and /DB with corresponding bit lines BL and /BL, respectively.

Spare column select gate SCSG has the same configuration as column select gate CSG. It electrically couples spare bit lines SBL and /SBL with data buses DB and /DB when spare column select line SCSL is activated to a selected state (of an H level).

The column select operation in MRAM device 1 is now described. The column select operation includes redundancy control for replacement/repair of the defective column(s).

FIG. 3 is a block diagram showing a configuration of redundancy control circuit 105 shown in FIG. 1. In FIG. 3, it is assumed by way of example that a defective address FAD is formed of (i+1) bits (i is a natural number) indicating a defective column including defective memory cell(s) in at least one of normal memory cells MC and dummy memory cells DMC. Defective address FAD is represented as FAD<0>, for example, to specify one of the bits. A plurality of defective address bits are represented as FAD<0:i>, for example, to collectively represent FAD<0> to FAD<i>. Herein, other signals formed of a plurality of bits, such as column address CA and row address RA, are represented in the same manner.

Referring to FIG. 3, address terminal 2 receives a column address CA including column address bits CA<0> to CA<i> comparable with defective address bits FAD<0:i>.

Redundancy control circuit 105 includes matching/comparing gates 107-0 to 107-i provided corresponding to column address bits CA<0> to CA<i>, and logic gates 108 and 109. Program circuit 100 provides redundancy control circuit 105 with defective address FAD formed of defective address bits FAD<0:i> and a redundant column activating signal ACT. Redundant column activating signal ACT is set to an H level, based on the information stored in program circuit 100 in a non-volatile manner, when use of the redundant column is designated for replacement/repair of the defective memory cell(s). When there is no defective memory cell in the normal memory cells and the dummy memory cells, redundant column activating signal ACT is maintained at an L level.

Matching/comparing gates 107-0 to 107-i match/compare column address CA<0:i> with defective address FAD<0:i>. For example, matching/comparing gate 107-0 compares column address bit CA<0> with defective address bit FAD<0>, and outputs a signal of an H level when they match with each other, and outputs a signal of an L level when they mismatch. Logic gate 108 outputs an AND operation result of the outputs of matching/comparing gates 107-0 to 107-i. Logic gate 109 performs an AND operation of the output of logic gate 108 and the redundant column activating signal ACT from program circuit 100, and outputs the result as a spare enable signal SE.

Thus, the output of logic gate 108 is set to an H level when column address bits CA<0:i> and defective address bits FAD<0:i>, or column address CA and defective address FAD, completely match with each other. Spare enable signal SE output from logic gate 109 is set to an H level when use of the redundant column is designated and defective address FAD and column address CA match with each other.

Although not shown, an inverse signal of spare enable signal SE is transmitted to column decoder 25 as a normal enable signal. When the normal enable signal is set to an H level, column decoder 25 activates one of column select lines CSL1 CSLm to an H level based on column address CA, and inactivates spare column select line SCSL to an L level. On the contrary, when the normal enable signal is set to an L level, column decoder 25 activates spare column select line SCSL to an H level in response to spare enable signal SE, and inactivates each column select line CSL1 CSLm to an L level.

Referring again to FIG. 2, for each memory cell column, a transistor switch 62 for short-circuiting the other ends of corresponding bit lines BL and /BL, and a control gate 66 for controlling on/off of transistor switch 62 are provided. In FIG. 2, transistor switches 62-1 and 62-m corresponding to bit lines BL1, /BL1 and BLm, /BLm, and corresponding control gates 66-1 and 66-m are shown representatively. Each transistor switch 62 has a gate receiving the output of corresponding control gate 66. Each control gate 66 outputs an AND operation result of a voltage level of column select line CSL of the corresponding memory cell column and a control signal WE activated to an H level in the data write operation.

The similar configuration is provided for redundant column 11C. Specifically, a transistor switch 62-s is provided between the other ends of spare bit lines SBL and /SBL, and the gate of transistor switch 62-s receives an output of a control gate 66-s. Control gate 66-s outputs an AND operation result of the voltage levels of spare column select line SCSL and control signal WE.

Thus, in the data write operation, the ends of bit lines BL and /BL in a selected column corresponding to column address CA or the ends of spare bit lines SBL and /SBL in redundant column 11C are electrically coupled to each other by transistor switch 62.

Further, each bit line BL, /BL and each spare bit line SBL, /SBL are precharged to a ground voltage Vss by a precharge switch (not shown) in an active period of MRAM device 1, at least in a prescribed time period before the start of data read. During the data read operation and data write operation in the active period of MRAM device 1, the precharge switch is turned off, and each bit line BL, /BL and each spare bit line SBL, /SBL are separated from ground voltage Vss (precharge voltage).

FIG. 4 shows operating waveforms during the data read operation and data write operation to illustrate replacement/repair in the MRAM device.

Firstly, the operation at the time of data read is described. Word line driver 30, in accordance with a result of row selection of row decoder 20, activates and connects write word line WWL corresponding to the selected row to power supply voltage Vcc2. Thus, a data write current Ip is passed through write word line WWL of the selected row in a direction from word line driver 30 toward region 40. The data write current is not passed through write word line WWL of a non-selected row, as it is maintained in an inactive state (L level: ground voltage Vss).

When column address CA and defective address FAD mismatch, column select line CSL of the selected row is activated to a selected state (H level), and one ends of bit lines BL and /BL of the selected column are coupled to data buses DB and /DB, respectively. Further, corresponding transistor switch 62 turns on, and the other ends (opposite from the column select gate CSG side) of bit lines BL and /BL of the selected column are short-circuited.

When column address CA and defective address FAD match, spare column select line SCSL is activated to a selected state (H level), and one ends of corresponding spare bit lines SBL and /SBL, instead of bit lines BL and /BL of the selected column, are coupled to data buses DB and /DB, respectively. Further, transistor switch 62-s turns on and short-circuits the other ends (opposite from the spare column select gate SCSG side) of the spare bit lines SBL and /SBL.

Data write circuit 51W sets data buses DB and /DB to one and the other of power supply voltage Vcc2 (H level) and ground voltage Vss (L level). For example, when write data DIN has a data level of L level, a data write current -Iw for writing of L level data is passed through data bus DB. Data write current -Iw is supplied to bit line BL of the selected column or to spare bit line SBL via column select gate CSG or spare column select gate SCSG.

Data write current -Iw passed through bit line BL of the selected column or spare bit line SBL is turned or folded back by the corresponding transistor switch 62 having turned on. Thus, a data write current +Iw in the opposite direction is passed through the other bit line /BL or spare bit line /SBL. Data write current +Iw flowing through bit line /BL or-spare bit line/SBL is transmitted to data bus /DB via column select gate CSG or spare column select gate SCSG.

When write data DIN is at a data level of H level, the data write currents in the opposite directions can be passed through bit lines BL, /BL of the selected column or spare bit lines SBL, /SBL by reversing the voltage settings of data buses DB and /DB.

Thus, when column address CA and defective address FAD mismatch, a normal memory cell (selected memory cell) having data write currents passed through both corresponding write word line WWL and bit line BL (/BL) becomes a target to access, and data is written into the selected memory cell. By comparison, when column address CA and defective address FAD match, spare memory cell SMC belonging to the same memory cell row as the selected memory cell becomes a target to access. That is, by making the data write currents pass through both corresponding write word line WWL and spare bit line SBL (/SBL), data is written into spare memory cell SMC.

In the data write operation, read word lines RWL and dummy read word lines DRWL0, DRWL1 are maintained in a non-selected state (L level).

Next, the data read operation is described.

At the time of data read, word line driver 30 activates read word line RWL corresponding to a selected row to an H level in accordance with the result of row selection of row decoder 20. In a non-selected row, the voltage level of read word line RWL is maintained in an inactive state (L level). Further, one of dummy read word lines DRWL0, DRWL1 is activated to an H level at a timing similar to that of read word line RWL of the selected row, according to whether the selected row is an even row or an odd row, as described above.

At the start of data read, read word line RWL of the selected row is activated to an H level, and corresponding access transistors ATR turn on. Then, normal memory cells MC and spare memory cell SMC corresponding to the selected row are electrically connected between bit line BL, /BL and spare bit line SBL, /SBL and ground voltage Vss, respectively, via access transistor