Thin film transistor and manufacturing method thereof Number:7,410,839 from the United States Patent and Trademark Office (PTO) owispatent The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.<H manufacturing, transistor, Thin, film, trans, 7410839.html, Patent, pto, 7410839

Title: Thin film transistor and manufacturing method thereof

Abstract: The present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a semiconductor device which realizes high-speed operation and high-performance of the semiconductor device and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method in which a manufacturing process is simplified. The semiconductor device of the present invention has an island-shaped semiconductor film formed over a substrate having an insulating surface and a gate electrode formed over the island-shaped semiconductor film, in which the gate electrode is oxidized its surface by high-density plasma to be slimmed and the substantial length of a channel is shortened.

Patent Number: 7,410,839 Issued on 08/12/2008 to Isobe, et al.

Inventors: Isobe; Atsuo (Atsugi, JP), Yamazaki; Shunpei (Setagaya, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd. (Kanagawa-ken, JP)

Appl. No.: 11/410,071

Filed: April 25, 2006

Foreign Application Priority Data


Apr 28, 2005 [JP]			2005-133661

Current U.S. Class: 438/149 ; 257/347; 257/57; 257/E21.134; 257/E21.212; 257/E21.414; 438/151; 438/166; 438/197; 438/795; 438/798

Current International Class: H01L 21/84 (20060101); H01L 21/00 (20060101); H01L 21/336 (20060101); H01L 21/8234 (20060101)

Field of Search: 438/149,151,166,197,795,798 257/347,57,E21.134,E21.212,E21.414

References Cited [Referenced By]

U.S. Patent Documents


5485019	January 1996	Yamazaki et al.
5956581	September 1999	Yamazaki et al.
6426245	July 2002	Kawasaki et al.
6534826	March 2003	Yamazaki
6555420	April 2003	Yamazaki
6716761	April 2004	Mitsuiki
6773996	August 2004	Suzawa et al.
6818852	November 2004	Ohmi et al.
6975018	December 2005	Ohmi et al.
2002/0020497	February 2002	Ohmi et al.
2004/0050494	March 2004	Ohmi et al.
2004/0217431	November 2004	Shimada
2006/0154492	July 2006	Ide et al.
2006/0246633	November 2006	Arai et al.
2006/0246640	November 2006	Kuwashima et al.
2006/0246644	November 2006	Isobe et al.
2006/0246738	November 2006	Isobe et al.

Foreign Patent Documents


1 617 483	Jan., 2006	EP
1 622 194	Feb., 2006	EP
2002-217170	Aug., 2002	JP
2005-093737	Apr., 2005	JP
WO 2004/017396	Feb., 2004	WO

Other References

The Advancing Introduction of Plasma Oxynitriding Apparatus Adopted by More Than 10 LSI Makers, Nikkei Microdevices, Apr. 2005, pp. 100-103. cited by other.

Primary Examiner: Lebentritt; Michael S.
Assistant Examiner: Ahmadi; Mohsen
Attorney, Agent or Firm: Robinson; Eric J. Robinson Intellectual Property Law Office, P.C.

Claims

What is claimed is:

1. A method for manufacturing a thin film transistor comprising the steps of: forming an amorphous semiconductor film over a substrate having an insulating surface; forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film; forming an island-shaped semiconductor film by etching the crystalline semiconductor film; forming a gate insulating film over the island-shaped semiconductor film; forming a conductive film over the gate insulating film; forming a gate electrode by etching the conductive film; and slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma.

2. The method according to claim 1, wherein a high electron density of the high-density plasma is 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3 and an electron temperature is 0.5 to 1.5 eV.

3. The method according to claim 1, wherein the surface of the gate electrode is oxidized using a mixed gas of oxygen, hydrogen, and argon in the slimming step.

4. The method according to claim 1, wherein an oxide film formed on the surface of the gate electrode contains a rare gas element.

5. A method for manufacturing a thin film transistor comprising the steps of: forming an amorphous semiconductor film over a substrate having an insulating surface; forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film; forming an island-shaped semiconductor film by etching the crystalline semiconductor film; forming a gate insulating film over the island-shaped semiconductor film; forming a conductive film over the gate insulating film; forming a gate electrode by etching the conductive film; slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma; and removing an oxide film formed over the surface of the gate electrode.

6. The method according to claim 5, wherein a high electron density of the high-density plasma is 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3 and an electron temperature is 0.5 to 1.5 eV.

7. The method according to claim 5, wherein the surface of the gate electrode is oxidized using a mixed gas of oxygen, hydrogen, and argon in the slimming step.

8. A method for manufacturing a thin film transistor comprising the steps of: forming an amorphous semiconductor film over a substrate having an insulating surface; forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film; forming an island-shaped semiconductor film by etching the crystalline semiconductor film; forming a gate insulating film over the island-shaped semiconductor film; forming a conductive film over the gate insulating film; forming a gate electrode by etching the conductive film; slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma; doping the island-shaped semiconductor film with first impurity ion using the gate electrode as a mask; forming a sidewall on a side surface of the gate electrode; and doping the island-shaped semiconductor film with second impurity ion to have a higher concentration of that of the first impurity ion, using the gate electrode and the sidewall as a mask.

9. The method according to claim 8, wherein a high electron density of the high-density plasma is 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3 and an electron temperature is 0.5 to 1.5 eV.

10. The method according to claim 8, wherein the first impurity ion and the second impurity ion are a same impurity ion.

11. The method according to claim 8, wherein the surface of the gate electrode is oxidized using a mixed gas of oxygen, hydrogen, and argon in the slimming step.

12. The method according to claim 8, wherein an oxide film formed on the surface of the gate electrode contains a rare gas element.

13. A method for manufacturing a thin film transistor comprising the steps of: forming an amorphous semiconductor film over a substrate having an insulating surface; forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film; forming an island-shaped semiconductor film by etching the crystalline semiconductor film; forming a gate insulating film over the island-shaped semiconductor film; forming a conductive film over the gate insulating film; forming a gate electrode by etching the conductive film; slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma; removing an oxide film formed over the surface of the gate electrode; doping the island-shaped semiconductor film with first impurity ion using the gate electrode as a mask; forming a sidewall on a side surface of the gate electrode; and doping the island-shaped semiconductor film with second impurity ion to have a higher concentration of that of the first impurity ion, using the gate electrode and the sidewall as a mask.

14. The method according to claim 13, wherein a high electron density of the high-density plasma is 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3 and an electron temperature is 0.5 to 1.5 eV.

15. The method according to claim 13, wherein the first impurity ion and the second impurity ion are a same impurity ion.

16. The method according to claim 13, wherein the surface of the gate electrode is oxidized using a mixed gas of oxygen, hydrogen, and argon in the slimming step.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a thin film transistor, one feature of which is a manufacturing method of a gate electrode, and the manufacturing method thereof. More specifically, the present invention relates to a semiconductor device such as an ID chip, an RFID, a CPU (central processing unit), a liquid crystal display device, and an organic EL display device, and a manufacturing method thereof.

2. Description of the Related Art

In recent years, an electronic appliance of a semiconductor device such as an ID chip, an RFID, a CPU, a liquid crystal display device, and an organic EL display device has been actively developed. In order to realize high integration and high-speed operation of a semiconductor device, miniaturization of the semiconductor device in a manufacturing process is required.

As a method of manufacturing such a semiconductor device, a method in which a gate electrode is miniaturized by etching, or a method in which a surface of a gate electrode is oxidized by using an anodic oxidation method to shorten a substantial length of a channel can be given (see Patent Document 1).

[Patent Document 1] Japanese Patent Application Laid-Open No. 2002-217170

SUMMARY OF THE INVENTION

There is limitation in miniaturization of a gate electrode in terms of precision or the like when using a conventional etching method. In addition, there is a problem that when miniaturization is conducted only by etching, the number of manufacturing steps is significantly increased (see Patent Document 1).

Further in addition, when miniaturization of a gate electrode is conducted by oxidizing a surface of the gate electrode using an anodic oxidation, a step of dividing the gate electrodes is required after making all the gate electrodes capable of being connected at the same electrical potential. Therefore, the number of manufacturing steps of the semiconductor device is significantly increased, which is a problem.

In view of the foregoing, the present invention provides a thin film transistor in which a substantial length of a channel is shortened to miniaturize a semiconductor device and a manufacturing method thereof. In addition, the present invention provides a thin film transistor which realizes high-speed operation and high-performance of a semiconductor device by shortening a substantial length of a channel and a manufacturing method thereof. Further in addition, it is an object of the present invention to provide a manufacturing method of a thin film transistor in which a manufacturing process is simplified.

One manufacturing method for a thin film transistor according to the present invention comprises, forming an amorphous semiconductor film over a substrate having an insulating surface, forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film, forming an island-shaped semiconductor film by etching the crystalline semiconductor film, forming a gate insulating film over the island-shaped semiconductor film, forming a conductive film over the gate insulating film, and forming a gate electrode by etching the conductive film, wherein the gate electrode is slimmed by oxidizing a surface of the gate electrode using high-density plasma.

One manufacturing method for a thin film transistor according to the present invention comprises, forming an amorphous semiconductor film over a substrate having an insulating surface, forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film, forming an island-shaped semiconductor film by etching the crystalline semiconductor film, forming a gate insulating film over the island-shaped semiconductor film, forming a conductive film over the gate insulating film, forming a gate electrode by etching the conductive film, and slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma, wherein an oxide film formed over the surface of the gate electrode is removed.

One manufacturing method for a thin film transistor according to the present invention comprising, forming an amorphous semiconductor film over a substrate having an insulating surface, forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film, forming an island-shaped semiconductor film by etching the crystalline semiconductor film, forming a gate insulating film over the island-shaped semiconductor film, forming a conductive film over the gate insulating film, forming a gate electrode by etching the conductive film, slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma, doping the island-shaped semiconductor film with an impurity ion using the gate electrode as a mask, and forming a sidewall on a side surface of the gate electrode, wherein the island-shaped semiconductor film is doped with an impurity ion to have a higher concentration of that of the impurity ion which is added in advance, using the gate electrode and the sidewall as a mask.

One manufacturing method for a thin film transistor according to the present invention comprises, forming an amorphous semiconductor film over a substrate having an insulating surface, forming a crystalline semiconductor film by crystallizing the amorphous semiconductor film, forming an island-shaped semiconductor film by etching the crystalline semiconductor film, forming a gate insulating film over the island-shaped semiconductor film, forming a conductive film over the gate insulating film, forming a gate electrode by etching the conductive film, slimming the gate electrode by oxidizing a surface of the gate electrode using high-density plasma, removing an oxide film formed over the surface of the gate electrode, doping the island-shaped semiconductor film with an impurity ion using the gate electrode as a mask, and forming a sidewall on a side surface of the gate electrode, wherein the island-shaped semiconductor film is doped with an impurity ion to have a higher concentration of that of the impurity ion which is added in advance, using the gate electrode and the sidewall as a mask.

High-density plasma of the present invention has an electron density of 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3 and an electron temperature is 0.5 to 1.5 eV.

A thin film transistor according to the present invention comprises a substrate having an insulating surface and an island-shaped semiconductor device formed over the substrate, wherein an oxide film is formed over a surface of the gate electrode by using high-density plasma, and the oxide film contains a rare gas element.

A thin film transistor according to the present invention comprises a substrate having an insulating surface and an island-shaped semiconductor device having an LDD region formed over the substrate, wherein an oxide film is formed over a surface of the gate electrode by using high-density plasma, and the oxide film contains a rare gas element.

According to the present invention, a substantial length of a channel can be shortened by oxidizing a surface of a gate electrode. Therefore, miniaturization of a semiconductor device and decrease in gate potential can be realized. Therefore, high-speed operation and high-performance of a semiconductor device can be realized.

In addition, according to the present invention, a precise oxide film can be formed over the surface of the gate electrode simply compared with the conventional art, so that a manufacturing process can be simplified.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A to 1F are cross-sectional views for showing a manufacturing process of a thin film transistor of the present invention;

FIGS. 2A to 2D are cross-sectional views for showing a manufacturing process of a thin film transistor of the present invention;

FIGS. 3A to 3C are cross-sectional views for showing a manufacturing process of a thin film transistor of the present invention;

FIG. 4 is a cross sectional view of a plasma apparatus used in the present invention;

FIGS. 5A and 5B are cross-sectional views for showing a manufacturing process of a semiconductor device of the present invention;

FIGS. 6A to 6F are cross-sectional views for showing a manufacturing process of a semiconductor device of the present invention;

FIG. 7 is a top view of a plasma apparatus used in the present invention;

FIGS. 8A to 8D are cross-sectional views for showing a manufacturing process of a semiconductor device of the present invention;

FIGS. 9A and 9B are cross-sectional views for showing a manufacturing process of a semiconductor device of the present invention;

FIGS. 10A to 10E show semiconductor devices of the present invention;

FIG. 11 is a block diagram of a CPU using a semiconductor device of the present invention;

FIG. 12 is a cross-sectional view for showing a manufacturing process of a display device of the present invention;

FIG. 13 is a top view for showing a display device of the present invention;

FIGS. 14A and 14B are cross-sectional views for showing a manufacturing process of a liquid crystal display device of the present invention;

FIG. 15 is a cross-sectional view for showing a manufacturing process of a liquid crystal display device of the present invention;

FIGS. 16A to 16D are views for electric appliances using a semiconductor device of the present invention;

FIGS. 17A and 17B are cross-sectional views for showing a manufacturing process of a thin film transistor of the present invention;

FIGS. 18A and 18B are cross-sectional views for showing a manufacturing process of a thin film transistor of the present invention;

FIGS. 19A to 19D are views for showing a manufacturing process of a semiconductor device of the present invention; and

FIGS. 20A to 20C are views for showing a manufacturing process of a semiconductor device of the present invention.

DETAILED DESCRIPTION OF THE INVENTION

Embodiment Mode

Hereinafter, the embodiment modes of the present invention will be described with reference to the accompanying drawings. The present invention can be carried out in many different modes, and it is easily understood by those skilled in the art that modes and details herein disclosed can be modified in various ways without departing from the purpose and the scope of the present invention. It should be noted that the present invention should not be interpreted as being limited to the description of the embodiment modes to be given below. Note that in the drawings, the same reference numerals are used for the same portions or the portions having the same functions, and the description thereof is not made repeatedly.

In addition, Embodiment Modes 1 to 7 described below can be arbitrarily combined within a practicable range.

Embodiment Mode 1

In this embodiment mode, a manufacturing process of a thin film transistor in which a gate electrode is formed over a substrate having an insulating surface and the gate electrode is slimmed (hereinafter, abbreviated to a thin film transistor), is explained with reference to FIGS. 1A to 1F, 2A to 2D, and 3A to 3C. It is to be noted that in this specification, slimming and miniaturizing are considered to have the same meaning. In addition, in this specification, slimming of an electrode is considered to oxidize an electrode in a thickness of 3 to 50 nm from the surface of the electrode. In this specification, a gate electrode is formed to have a witdth of 50 nm to 1 .mu.m and the width of the formed gate electrode is reduced by 10% or more by slimming. That is, the gate electrode is oxidized.

A base film 101 is formed to have a thickness of 100 to 300 nm over a substrate 100. As the substrate 100, an insulating substrate such as a glass substrate, a quartz substrate, a plastic substrate, a ceramic substrate, and the like; a metal substrate; a semiconductor substrate; and the like can be used.

As the base film 101, a single layer structure of an insulating film containing oxygen or nitrogen such as silicon oxide, silicon nitride, silicon oxide containing nitrogen, and silicon nitride containing oxygen; or a stacked layer structure formed by combing films of those materials can be employed. Here, silicon oxide is used as the base film.

The base film 101 is provided in order to prevent alkali metal such as Na and alkaline earth metal contained in the substrate 100 from diffusing into a semiconductor and from causing an adverse effect on a characteristic of a semiconductor element. In the case where the substrate 100 is a substrate which contains any amount of alkali metal or alkaline earth metal such as a glass substrate or a plastic substrate, it is effective to provide the base film in order to prevent impurity diffusion. However, when a quartz substrate which does not lead a severe problem of impurity diffusion is used, the base film 101 is not necessarily provided.

A semiconductor film 102 is formed to have a thickness of 10 to 100 nm over the base film 101 (FIG. 1A). A material for the semiconductor film can be selected in accordance with the required characteristics of the thin film transistor, and any of a silicon film, a silicon germanium film, and a silicon carbide film may be used. Here, silicon is used. In the case of using silicon germanium, the concentration of germanium is preferably in the range of approximately 0.01 to 4.5 atomic %. As the semiconductor film, a crystalline semiconductor film that is crystallized by a laser crystallization method using an excimer laser or the like after forming an amorphous semiconductor film or a microcrystal semiconductor film by a sputtering method, an LPCVD method, a plasma CVD method, or the like is preferably used. Alternatively, a semiconductor film may be also crystallized by treating the semiconductor film with heat plasma which is generated by applying DC bias. The microcrystal semiconductor film can be obtained by glow discharge decomposition of a gas containing silicon such as SiH.sub.4. The microcrystal semiconductor film can be easily formed by diluting the gas containing silicon with hydrogen, fluorine, or any of the rare gas elements with hydrogen or fluorine.

In addition, it is also possible to apply a rapid thermal annealing method (an RTA method) using a halogen lamp or a crystallization technique using a heating furnace as the crystallization technique. Further, a method in which a metal element such as nickel is added into an amorphous semiconductor film to cause solid-phase growth with the added metal as a crystal nucleus may also be used.

Then, an island-shaped semiconductor film 103 is formed by etching the semiconductor film. A gate insulating film 104 is formed to have a thickness of 2 to 200 nm so as to cover the island-shaped semiconductor film 103 (FIG. 1B). The gate insulating film 104 may have a stacked layer structure formed by appropriately combining any of films of silicon oxide, silicon nitride, silicon oxide containing nitrogen, or silicon nitride containing oxygen, and the like by a CVD method or a sputtering method.

Then, a conductive film 105 which serves as a gate electrode is formed by a sputtering method to have a thickness of 150 to 500 nm over the gate insulating film 104. As the conductive film 105, an aluminum (Al) film, a tungsten (W) film, a molybdenum (Mo) film, or the like can be used. Here, a tungsten film is used as the conductive film.

Then, a resist 106 is formed over the conductive film by photolithography using a photo mask (FIG. 1C).

Then, etching is conducted using the resist 106 as a mask (FIG. 1D), thereby the conductive film 105 is etched to be a gate electrode 107. After forming the gate electrode, the resist 106 is removed (FIG. 1D).

In this embodiment mode, a mixed gas of Cl.sub.2, SF.sub.6, and O.sub.2 is used as an etching gas, and the mixture ratio of Cl.sub.2:SF.sub.6:O.sub.2 is 33:33:10 sccm. Plasma is generated by applying a power of 2000 W to a coil-shaped electrode at a pressure of 0.67 Pa. A power of 50 W is applied to a substrate side (sample stage).

Subsequently, the surface of the gate electrode 107 is oxidized and the gate electrode 107 is slimmed, thereby a gate electrode 108 covered with an oxide film (hereinafter, referred to as a gate electrode 108) is formed (FIG. 1E). The oxide film is formed over the surface of the gate electrode 107 by oxidation using a high-density plasma apparatus. Therefore, a substantial length of a channel can be shortened.

Note that by providing an oxide film over the surface of the gate electrode 108, an offset region is formed between the end of the gate electrode and an impurity region formed in the island-shaped semiconductor film in a subsequent step. When the offset region is not necessary, the oxide film over the surface of the gate electrode may be removed.

In this embodiment mode, a high-density plasma apparatus is used. FIG. 4 shows one example of a high-density plasma apparatus. A treatment chamber is evacuated to vacuum and a gas containing oxygen is introduced through a gas introduction opening 65. In this embodiment mode, a mixed gas of oxygen (O.sub.2), hydrogen (H.sub.2), and argon (Ar) is used. It is to be noted that the mixed gas to be introduced may contain 0.1 to 100 sccm of oxygen, 0.1 to 100 sccm of hydrogen, and 100 to 5000 sccm of argon. It is to be noted that the mixed gas to be introduced preferably has the mixture ratio of oxygen:hydrogen:argon is 100:1:1. For example, a mixed gas to be introduced may contain 5 sccm of oxygen, 5 sccm of hydrogen, and 500 sccm of argon. Although argon is used in this embodiment mode, another rare gas may be used. Next, the insulating substrate 100 to which has the gate electrode 107 thereover is placed over a support table 64 having a heating mechanism to heat the insulating substrate 100 to 400.degree. C. It is to be noted that the insulating substrate 100 may be heated to 200 to 550.degree. C. (preferably, 250.degree. C. or more). When a plastic substrate is used as the substrate 100, the substrate with a glass transition point of 200.degree. C. or more is needed to be used and the substrate is heated to a temperature of the glass transition point or less. The distance between the insulating substrate 100 and an antenna 62 is 20 to 80 nm (preferably, 20 to 60 nm).

Next, a microwave is applied from a waveguide 60 to the antenna 62. In this embodiment mode, a microwave with a frequency of 2.45 GHz is applied. The microwave applied from the antenna 62 is introduced to the treatment chamber through a dielectric plate 63 in the treatment chamber, thereby high-density plasma 66 containing an oxygen gas, a hydrogen gas, and an argon gas is generated. In the high-density plasma 66 containing the oxygen gas, the hydrogen gas, and the argon gas; the argon gas is excited by the introduced microwave to generate Ar radical. Then Ar radical in an intermediate excited state collides with oxygen molecules and hydrogen molecules to form OH radical. The OH radical reacts with a material of the gate electrode to form an oxide film on the surface of the gate electrode 107. In this embodiment mode, since molybdenum is used for the gate electrode, a molybdenum oxide film is formed on the surface of the gate electrode. The oxygen gas, the hydrogen gas, and the argon gas used in this step are exhausted outside the treatment chamber through an exhaust port 67.

The plasma generated using the plasma apparatus as shown in FIG. 4 has a low electron temperature (1.5 eV or less (preferably, 0.5 to 1.5 eV)), and a high electron density (1.0.times.10.sup.11 cm.sup.-3 or more (preferably, 1.0.times.10.sup.11 cm.sup.-3 to 1.0.times.10.sup.13 cm.sup.-3). Therefore, an oxide film with little plasma damage can be formed at a low temperature.

It is suggested that a rare gas is contained in the oxide film in this step. Therefore, a sample to which the plasma treatment of this step is conducted to form an oxide film is manufactured over a substrate and a measurement thereof using TXRF is conducted. Here, Ar is used as the rare gas for the plasma treatment. As the result of the measurement, a concentration of Ar contained in the oxide film is approximately 1.times.10.sup.15 to 1.times.10.sup.16 atoms/cm.sup.3. Therefore, the rare gas used for high-density plasma treatment is contained in the oxide film which is formed in this step at the similar concentration (1.times.10.sup.15 to 1.times.10.sup.16 atoms/cm.sup.3).

In addition, there is a possibility that a dust is attached over the film formed by a CVD method and a sputtering method. There is another possibility that a part of resist is remained over the surface of the gate electrode in the step of removing the resist after etching the gate electrode. FIG. 5A shows a state in which a dust 1501 is attached to the surface of the gate electrode. A case in which plasma oxidation of this embodiment mode is conducted to the gate electrode 107 with the dust attached thereover is described.

By conducting the plasma oxidation of this embodiment mode, the surface of the gate electrode is oxidized not only the part without dust but also the part where the dust 1501 is attached (FIG. 5B). The volume of the dust 1501 is increased due to oxidation of the surface or the whole part of the dust 1501. Therefore, the dust 1501 can be removed from the surface of the gate electrode 108 having the oxide film by a simple cleaning process such as a brush cleaning. That is, removing of a dust even at the nanolevel becomes easier by plasma oxidation.

Next, doping of an impurity ion is conducted to the island-shaped semiconductor film 103 (FIG. 1F) to form a low-concentration impurity region. The island-shaped semiconductor film 103 is doped with an impurity element through the gate insulating film to form low-concentration impurity regions 110a and 110b in the island-shaped semiconductor film. In addition, a channel-formation region 111 is also formed. The element concentrations of each of the low-concentration impurity regions 110a and 110b is 1.times.10.sup.16 to 1.times.10.sup.20 atoms/cm.sup.3 (preferably, 1.times.10.sup.16 to 5.times.10.sup.18 atoms/cm.sup.3). As a doping method, an ion doping method or an ion implantation method can be used. In order to manufacture a p-type semiconductor, for example, boron (B), gallium (Ga), or the like is used, whereas phosphorus (P), arsenic (As), or the like is used in order to manufacture an n-type semiconductor.

Next, an insulating layer is formed so as to cover the gate insulating film 104 and the gate electrode 108. The insulating layer is formed by sequentially forming a silicon oxide film containing nitrogen by a plasma CVD method to have a thickness of 100 nm, and forming a silicon oxide film by a thermal CVD method to have a thickness of 200 nm.

Subsequently, the insulating layer is selectively etched by anisotropic etching mainly in a perpendicular direction to form a insulating layer (hereinafter referred to as a sidewall) 201 which is in contact with a side surface of the gate electrode 108 (FIG. 2A). The sidewall 201 is used as a mask to form silicide in a subsequent step over a source region and a drain region. In addition, by this etching, a part of the gate insulating film is also removed to form a gate insulating film 202 so as to expose a part of the semiconductor film. The exposed parts of the semiconductor film become the source region and the drain region later. When an etching selective ratio of the insulating film and the semiconductor film is low, the exposed semiconductor film is etched to some extent, and the film thickness thereof becomes thin.

Next, a metal film 203 is formed to cover the exposed part of the semiconductor film, the sidewall 201, and the gate electrode 108 (FIG. 2B). The metal film 203 is formed from a material which reacts with the semiconductor film to form silicide. As the metal film, for example, a nickel film, a titanium film, a cobalt film, a platinum film, or a film containing an alloy having at least two kinds of these elements, or the like can be given. In this embodiment mode, a nickel film is used as the metal film. The nickel film is formed by sputtering at a room temperature by deposition power of 500 W to 1 kW.

After the nickel film is formed, silicide layers 204a and 204b, low-concentration impurity regions 205a and 205b are formed by heat treatment. In this embodiment mode, the silicide layers 204a and 204b become nickel silicide. As the heat treatment, RTA, furnace annealing, or the like can be used. At this time, by controlling a film thickness of the metal film, a heating temperature, and a heating time; a structure in which only the surface of the semiconductor layer becomes silicide or a structure in which the whole part of the semiconductor layer becomes silicide is formed. For example, the structure shown in FIG. 2C can be obtained by forming the metal film so as to have a film thickness that is equal to or more than half of that of the semiconductor film, by forming the metal film with a higher heating temperature, or by forming the metal film with a longer heating time.

Then, nickel which has not reacted is removed. Here, nickel which has not reacted is removed by using an etching solution containing HCl, HNO.sub.3, and H.sub.2O at a ratio of 3:2:1.

Then, an interlayer insulating film 206 is formed. The interlayer insulating film 206 is formed by using an organic material or an inorganic material. The interlayer insulating film 206 may have a single layer structure or a stacked layer structure. A contact hole is formed in the interlayer insulating film 206 by etching so that the silicide layers 204a and 204b, which serve as the source region or the drain region later, are exposed. Then, a conductive layer may be formed to fill the contact hole and the conductive layer may be etched to form a wiring 207.

On the other hand, when a structure in which only the surface of the semiconductor layer becomes silicide is employed, unlike the structure shown in FIG. 2C, doping of an impurity ion may be conducted to the semiconductor layer to form a high-concentration impurity region using the sidewall 201 as a mask in FIG. 3B after silicide layers 301a and 301b are formed over the surface of the semiconductor layer in a step shown in FIG. 3A. High-concentration impurity regions 302a and 302b which serve as the source region and the drain region later are formed by the doping. The doping is conducted so that each high-concentration impurity region has an impurity element concentration of 1.times.10.sup.9 to 1.times.10.sup.21 atoms/cm.sup.3. At the same time, a low-concentration impurity region is also formed. As a doping method, an ion doping method or an ion implantation method can be used. In order to manufacture a p-type semiconductor, boron (B), gallium (Ga), or the like is used, whereas phosphorus (P), arsenic (As), or the like is used in order to manufacture an n-type semiconductor.

Then, the impurity is activated and the interlayer insulating film 206 is formed as in the case of shown in FIGS. 2A to 2D in which the silicide layers are formed in the whole part of the semiconductor layer. The interlayer insulating film 206 is formed by using an organic material or an inorganic material. The interlayer insulating film 206 may have a single layer structure or a stacked layer structure. A contact hole is formed in the interlayer insulating film 206 by etching so that the silicide layers 205a and 205b, which serve as the source region or the drain region later, are exposed. Then, a conductive layer may be formed to fill the contact hole and the conductive layer may be etched to form a wiring.

Before the interlayer insulating film is formed, or after a first layer or a second layer of the interlayer insulting film is formed in the case of the interlayer insulating film has a stacked layer structure, thermal activation of the impurity regions may be conducted. Laser light irradiation, RTA, heat treatment using a furnace or the like can be used as the thermal activation. Since silicide is used to form an ohmic contact of the impurity region and a wiring in this structure, a step of thermal activation of the impurity region can be omitted.

When the structure of FIG. 3C is compared with the structure of FIG. 2D, an area in which the silicide layers 301a and 301b are in contact with a part of the semiconductor film that is not silicide, is larger than that of the structure of FIG. 2D. Therefore, contact resistance of the silicide layers 301a and 301b and the part of the semiconductor film other than the silicide layer becomes low, so that parasitic resistance is lower than that of the structure of FIG. 2D.

On the other hand, when the structure of FIG. 2D is compared with the structure of FIG. 3C resistance of the source region and the drain region is lower. In addition, since a step of doping of an impurity ion for forming the high-concentration impurity region is not required, the number of manufacturing steps for forming the structure of FIG. 2D is smaller than that of the structure of FIG. 3C.

In FIGS. 3A to 3C, doping of the impurity ion for forming the high-concentration impurity region is conducted after forming the silicide; however, the metal film 203 may be provided to form silicide after doping of the impurity ion. In addition, in order to form the structure of FIG. 3C, the silicide layers 301a and 301b may be formed after doping of the impurity ion by using the sidewall 201 as a mask.

In the thin film transistor formed according to this embodiment mode having a structure above described, a substantial length of a channel can be shortened. Therefore, a gate electrode can be miniaturized and a gate capacitance can be reduced, thereby high-speed operation and high-performance of the semiconductor device can be realized. In addition, the manufacturing process can be simplified.

A structure of the thin film transistor is not limited to a single-gate structure having one channel formation region as shown in this embodiment mode. The structure may be a multi gate structure with a plurality of channel formation regions. For example, a double-gate structure having two channel formation regions or a triple-gate structure having three channel formation regions may be employed. In addition, a transistor in a peripheral driver circuit region may have a single-gate structure or a multi-gate structure such as a double-gate structure or a triple-gate structure.

It is to be noted that the present invention is not limited to the manufacturing method of a thin film transistor described in this embodiment mode, but can also be applied to a top gate type (planar type), a bottom gate type (inversed staggered type), or a dual gate type in which two gate electrodes are respectively arranged at the top and bottom of a channel formation region, each with a gate insulating film interposed therebetween, or other structures.

Embodiment Mode 2

In this embodiment mode, a method of hydrogenation of a semiconductor layer is described with reference to FIGS. 17A, 17B, 18A, and 18B. It is to be noted that the thin film transistor used in this embodiment mode is manufactured by the same method as that of the structure of FIGS. 1A to 1F in Embodiment Mode 1 and the same description is not made. In addition, in this embodiment mode, the same reference numerals in Embodiment Mode 1 are used for the same portions, and the detailed description thereof is not made repeatedly.

As shown in FIG. 1F in Embodiment Mode 1, a structure which has an impurity region and a channel formation region is manufactured. Then, an impurity element doped to the impurity region is activated. Laser light irradiation, RTA, heat treatment using a furnace, or the like can be used in the activation step.

Then, hydrogen plasma treatment is conducted using a high-density plasma apparatus to oxide a surface of a gate electrode. As a gas, hydrogen (H.sub.2) or a mixed gas of hydrogen (H.sub.2) and a rare gas is introduced. In this embodiment mode, the mixed gas of hydrogen (H.sub.2) and argon (Ar) is introduced.

Then, an insulating substrate 100 in which an impurity element is activated is heated to 350 to 450.degree. C. to conduct hydrogen plasma treatment using a high-density plasma apparatus. In this step, introduced hydrogen radical (H radical) reacts with the semiconductor layer and the gate insulating film to form a hydrogenated channel formation region 171 and impurity regions 170a and 170b which serve as a source region and a drain region (FIG. 17A).

It is to be noted that heat treatment may be conducted at 350 to 450.degree. C. in an atmosphere containing hydrogen after the hydrogen plasma treatment.

Then, an interlayer insulating film 206 is formed as in Embodiment Mode 1. The interlayer insulating film 206 is formed by using an organic material or an inorganic material. The interlayer insulating film 206 may have a single layer structure or a stacked layer structure. A contact hole is formed in the interlayer insulating film 206 by etching so that the impurity regions 170a and 170b, which serve as the source region or the drain region later, are exposed. Then, a conductive layer may be formed to fill the contact hole and the conductive layer may be etched to form a wiring 207 (FIG. 17B).

It is to be noted that the step of hydrogenation of the semiconductor layer requires to be conducted after the activation of the impurity because hydrogen is eliminated from the semiconductor layer when the semiconductor layer is heated to 500.degree. C. or more.

Then, a method of hydrogenation of the semiconductor layer with a slimmed gate electrode having a protective film thereover is described with reference to FIGS. 18A and 18B. It is to be noted that the thin film transistor used in this embodiment mode is manufactured by the same method as that of the structure of FIGS. 1A to 1F in Embodiment Mode 1 and the same description is not made. In addition, in this embodiment mode, the same reference numerals in Embodiment Mode 1 are used for the same portions, and the detailed description thereof is not made repeatedly.

As shown in FIG. 1F in Embodiment Mode 1, a structure which has an impurity region and a channel formation region is manufactured. Then, an impurity element doped to the impurity region is activated. Laser light irradiation, RTA, heat treatment using a furnace, or the like can be used as in the activation step.

Then, a protective film 175 is formed by a plasma CVD method so as to cover the gate electrode 108 and the gate insulating film 104. As the protective film, a silicon nitride film, a silicon nitride oxide film, or a silicon oxide nitride film is preferably used, but it is not limited thereto. In addition, the forming method is not limited to a plasma CVD method.

Then, hydrogen plasma treatment is conducted to the protective film 175 using a high-density plasma apparatus to oxide a surface of the gate electrode. As a gas, hydrogen (H.sub.2) or a mixed gas of hydrogen (H.sub.2) and a rare gas is introduced. In this embodiment mode, the mixed gas of hydrogen (H.sub.2) and argon (Ar) is introduced.

Then, the insulating substrate 100 with the protective film 175 formed thereover is heated to 350 to 450.degree. C. to conduct hydrogen plasma treatment using a high-density plasma apparatus. In this step, hydrogen radical (H radical) introduced to the protective layer 175 reacts with the semiconductor layer to form a hydrogenated channel formation region 171 and impurity regions 170a and 170b which serve as a source region and a drain region (FIG. 18A).

It is to be noted that ammonia (NH.sub.3) is introduced instead of hydrogen. In that case, NH radical reacts with a protective film to hydrogenate a semiconductor layer. At the same time, a nitride film (not shown) is formed over a protective film. Therefore, a film property of the protective film can be improved with a dense nitride film formed thereover.

It is to be noted that heat treatment may be conducted at 350 to 450.degree. C. in an atmosphere containing hydrogen after the hydrogen plasma treatment.

Then, an interlayer insulating film 206 is formed as in Embodiment Mode 1. The interlayer insulating film 206 is formed by using an organic material or an inorganic material. The interlayer insulating film 206 may have a single layer structure or a stacked layer structure. A contact hole is formed in the interlayer insulating film 206 by etching so that the impurity regions 170a and 170b, which serve as the source region or the drain region later, are exposed. Then, a conductive layer may be formed to fill the contact hole and the conductive layer may be etched to form a wiring 207 (FIG. 18B).

It is to be noted that the step of hydrogenation of the semiconductor layer requires to be conducted after the activation of the impurity because hydrogen is eliminated from the semiconductor layer when the semiconductor layer is heated to 500.degree. C. or more.

Embodiment Mode 3

In this embodiment mode, a method for forming a p-channel thin film transistor and an n-channel thin film transistor over one substrate is described with reference to FIGS. 6A to 6F. It is to be noted that the n-channel thin film transistor and the p-channel thin film transistor have the structure shown in FIG. 3C of Embodiment Mode 1. However, the structure is not limited thereto, and the structures of the thin film transistors in Embodiment Modes 1 and 2 are arbitrarily employed to the n-channel thin film transistor and the p-channel thin film transistor depending on the application. In addition, in this embodiment mode, the same reference numerals are used for the same portions as in Embodiment Modes 1 and 2, and a detailed explanation is omitted.

After an amorphous semiconductor film is formed over a substrate 100 and channel doping is conducted to the amorphous semiconductor film, the amorphous semiconductor film is crystallized by the same method as that of Embodiment Mode 1 to form a crystalline semiconductor film. Then, island-shaped semiconductor films 103a and 103b are formed by etching. The crystalline semiconductor film represents a crystalline silicon film here. In addition, as a base film 101 that is in contact with the substrate 100, a silicon nitride film containing oxygen is used.

Subsequently, a gate insulating film 104 is formed so as to cover the island-shaped semiconductor films 103a and 103b. As the gate insulating film 104, a silicon oxide film containing nitrogen is formed by a plasma CVD method. Then, gate electrodes 107a and 107b are formed by the same method as that of Embodiment Mode 1 over the island-shaped semiconductor films 103a and 103b, respectively.

Then, the surfaces of the gate electrode 107 are oxidized and the gate electrodes 107 are slimmed, thereby gate electrodes 108a and 108b each covered with an oxide film (hereinafter referred to as the gate electrodes 108a and 108b) are formed. The oxide film over the surface of the gate electrode is formed by the same method as that of Embodiment Mode 1. By this step, a substantial length of a channel can be shortened.

It is to be noted that the oxide film formed over the surface of the gate electrode may be removed.

By using the gate electrodes 108a and 108b as masks, the island-shaped semiconductor films 103a and 103b are doped with phosphorus that is an n-type impurity element to form low-concentration impurity regions by ion doping. Accordingly, in the island-shaped semiconductor film 103a, n-type low-concentration impurity regions 410a and 410b which do not overlap with the gate electrode 108a are formed and a channel formation region 111a is formed under the gate electrode 108a. Similarly, in the island-shaped semiconductor film 103b, n-type low-concentration impurity regions 411a and 411b which do not overlap with the gate electrode 108b are formed and a channel formation region 111b are formed under the gate electrode 108b. Doping of phosphorus is conducted so that the low-concentration impurity regions contain phosphorus at a concentration of 1.times.10.sup.16 to 5.times.10.sup.18 atoms/cm.sup.3 (FIG. 6A).

Subsequently, a resist mask 420 is formed so as to cover the island-shaped semiconductor film 103a and the gate electrode 108a. And then, by using the gate electrode 108b as a mask, the island-shaped semiconductor film 103b is doped with boron that is a p-type impurity element to form a low-concentration impurity region by ion doping. Accordingly, in the island-shaped semiconductor film 103b, p-type low-concentration impurity regions 411c and 411d which do not overlap with the gate electrode 108b are formed. Doping of boron is conducted so that the p-type low-concentration impurity regions contain boron at a concentration of 1.times.10.sup.18 to 1.times.10.sup.19 atoms/cm.sup.3. The p-type low-concentration impurity regions have been already doped with phosphorus and contains phosphorous in a low-concentration; however, a concentration of boron is higher than that of phosphorus, and n-type conductivity is converted by p-type conductivity (FIG. 6B).

Then, a sidewall is formed. A silicon oxide film is formed as an insulating film so as to cover the island-shaped semiconductor films 103a and 103b, and the gate electrodes 108a and 108b. Anisotropic dry etching is conducted to form a sidewall 201. Then, gate insulating films 412a and 412b are formed by etching the gate insulating film 104 using the sidewall 201 as a mask. Accordingly, each ends of the island-shaped semiconductor films 103a and 103b are exposed (FIG. 6C). When an etching selective ratio of the gate insulating film to the exposed part of the island-shaped semiconductor film is low, the island-shaped exposed semiconductor film is etched while forming the gate insulating films 412a and 412b, and a film thickness thereof becomes thin.

Next, by using the sidewalls 201 and the gate electrodes 108a and 108b as masks, the n-type low-concentration impurity regions 410a and 410b are doped with phosphorus that is an n-type impurity element in the self-alignment manner to form high-concentration impurity regions. Accordingly, n-type high-concentration impurity regions 414a and 414b are formed. The n-type high-concentration impurity regions 414a and 414b are doped with phosphorus so as to contain phosphorus at a concentration of 1.times.10.sup.20 to 1.times.10.sup.21 atoms/cm.sup.3. At the same time, n-type low-concentration impurity regions 413a and 414b are formed. Since a part of the p-type low-concentration impurity regions 411c and 411d is also doped with phosphorus so as to contain phosphorus at a high concentration, the exposed part of the island-shaped semiconductor film becomes n-type high-concentration impurity regions 416a and 416b. Further, by this doping, p-type low-concentration impurity regions 415a and 415b are formed in the island-shaped semiconductor film 103b.

Next, a resist mask 421 is formed so as to cover the island-shaped semiconductor film 103a, the gate electrode 108a, and the sidewall 201. And then, by using the gate electrode 108b and the sidewall 201 as masks, the exposed part of the island-shaped semiconductor film 103b is doped with boron that is a p-type impurity element in the self-alignment manner to form high-concentration impurity regions. Accordingly, p-type high-concentration impurity regions 416c and 416d are formed. The p-type high-concentration impurity regions have already been n-type high-concentration impurity regions doped with phosphorus, however, the n-type conductivity is converted by p-type conductivity by doping of boron. The p-type high-concentration impurity regions 416c and 416d are doped with boron by ion doping so as to contain boron at a concentration of 2.times.10.sup.20 to 5.times.10.sup.21 atoms/cm.sup.3. Thereafter, the resist mask 421 is removed (FIG. 6D).

Then, a metal film is formed over the entire surface so as to cover the exposed part of the semiconductor film, and heat treatment is conducted at a temperature at which the metal film and the semiconductor film react with each other and a silicide layer 440 is formed. The silicide layer 440 is formed over the surface of the p-type and n-type high-concentration impurity regions. In this embodiment mode, a nickel film is formed as the metal film, and nickel silicide is formed as the silicide layer 440. Thereafter, the metal film is removed (FIG. 6E).

Then, as a first layer of an interlayer insulating film, a silicon oxide film 450 containing nitrogen is formed to have a thickness of 50 nm.

Thereafter, activation of the formed impurity regions is conducted by heat treatment. Laser light irradiation, RTA, heat treatment using a furnace or the like can be used as the heat treatment. However, since silicide is formed to lower resistance of the source region and the drain region sufficiently in the present invention, a step of activation may be omitted.

A silicon nitride film 451 that is a second layer of the interlayer insulating film is formed to have a thickness of 100 nm and a silicon oxide film 453 that is a third layer of the interlayer insulating film is formed to have a thickness of 600 nm so as to be stacked sequentially. A contact hole reaching the silicide layers 440 is formed in the interlayer insulating film. Then, a titanium film having a thickness of 60 nm, a titanium nitride film having a thickness of 40 nm, an aluminum film having a thickness of 500 nm, a titanium film having a thickness of 60 nm, and a titanium nitride film having a thickness of 40 nm are stacked sequentially so as to fill the contact holes. Then, the stacked film is etched to form a wiring 454 which serves as a source electrode or a drain electrode (FIG. 6F).

By the foregoing process, an n-channel thin film transistor 460 and a p-channel thin film transistor 461 each having an LDD structure are formed. In the thin film transistor formed according to this embodiment mode having a structure above described, a substantial length of a channel can be shortened. Therefore, a gate electrode can be miniaturized and a gate capacitance can be reduced, thereby high-speed operation and high-performance of the semiconductor device can be realized. In addition, the manufacturing process can be simplified.

It is to be noted that in this embodiment mode, so-called counter doping, in which a semiconductor film of a p-channel thin film transistor is also doped with an n-type impurity element, is conducted; however, the method is not limited thereto. The semiconductor film 103b may be prevented from being doped with phosphorus by covering the p-channel thin film transistor with a resist mask or the like while conducting doping of phosphorus.

Embodiment Mode 4

In the foregoing embodiment modes, an example in which a thin film transistor having a gate electrode with an oxide surface is described. In this embodiment mode, a method of forming an oxide film over a surface of a gate electrode is described.

An example of an apparatus provided with a plurality of chambers is shown in FIG. 7. It is to be noted that FIG. 7 is a top view of a constitution example of an apparatus described in this embodiment mode.

The apparatus shown in FIG. 7 has a first chamber 1111, a second chamber 1112, a third chamber 1113, load lock chambers 1110 and 1115, and a common chamber 1120. Each chamber has airtightness and is provided with a vacuum evacuation pump and an inert gas introduction system.

The load lock chambers 1110 and 1115 are chambers for transferring a sample (a substrate to be processed) to a system. The first to third chambers 1111, 1112, and 1113 are chambers to perform etching, plasma treatment, or the like to a substrate 100. The common chamber 1120 is provided for the sample in common for the load lock chambers 1110 and 1115 and the first to third chambers. In addition, each of gate valves 1122 to 1126

are provided between the common chamber 1120 and the load lock chambers 1110 and 1115, and between the common chamber 1120 and the first to third chambers 1111 to 1113, respectively. It is to be noted that a robot arm 1121 is provided in the common chamber 1120, which transfers a substrate to be processed to each chamber.

As a specific example of forming a gate electrode 108 with an oxide surface by forming a conductive film 105 in the first chamber 1111, removing a resist 106 in the second chamber 1112, and oxidizing a surface of the gate electrode 107 in the third chamber 1113.

First, a cassette 1128 including a plurality of the substrates 100 is transferred to the load lock chamber 1110. After the cassette 1128 is transferred therein, a door of the load lock chamber 1110 is closed. After that, the gate valve 1122 is opened to take out one substrate to be processed from the cassette 1128, and then the substrate is disposed in the common chamber 1120 by the robot arm 1121. Alignment of the substrate 100 is performed in the common chamber 1120 at this time.

Then, the gate valve 1122 is clo