Total order comparator unit for comparing values of two floating point operands Number:7,133,890 from the United States Patent and Trademark Office (PTO) owispatent A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.<H comparator, comparing, Total, order, com, 7133890.html, Patent, pto, 7133890

Title: Total order comparator unit for comparing values of two floating point operands

Abstract: A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. The result can condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.

Patent Number: 7,133,890 Issued on 11/07/2006 to Steele, Jr.

Inventors: Steele, Jr.; Guy L. (Lexington, MA)
Assignee: Sun Microsystems, Inc. (Santa Clara, CA)

Appl. No.: 10/028,375

Filed: December 28, 2001

Current U.S. Class: 708/495

Current International Class: G06F 7/38 (20060101)

Field of Search: 708/495 340/146.2

References Cited [Referenced By]

U.S. Patent Documents


3725649	April 1973	Deerfield
4777613	October 1988	Shahan et al.
4788655	November 1988	Nakayama et al.
4991131	February 1991	Yeh et al.
5065352	November 1991	Nakano
5126963	June 1992	Fukasawa
5161117	November 1992	Waggener, Jr.
5249149	September 1993	Cocanougher et al.
5307303	April 1994	Briggs et al.
5347481	September 1994	Williams
5347482	September 1994	Williams
5357237	October 1994	Bearden et al.
5363321	November 1994	Dao Trong et al.
5365465	November 1994	Larson
5481489	January 1996	Yanagida et al.
5570310	October 1996	Smith
5666301	September 1997	Makino
5748516	May 1998	Goddard et al.
5812439	September 1998	Hansen
5862066	January 1999	Rossin et al.
5892697	April 1999	Brakefield
5931943	August 1999	Orup
5953241	September 1999	Hansen et al.
5963461	October 1999	Gorshtein et al.
5978901	November 1999	Luedtke et al.
5995991	November 1999	Huang et al.
6009511	December 1999	Lynch et al.
6049865	April 2000	Smith
6081823	June 2000	Purcell et al.
6105047	August 2000	Sharangpani et al.
6108772	August 2000	Sharangpani
6131106	October 2000	Steele, Jr.
6138135	October 2000	Karp
6151669	November 2000	Huck et al.
6189094	February 2001	Hinds et al.
6205460	March 2001	Steele, Jr.
6219685	April 2001	Story
6256655	July 2001	Ezer et al.
6286023	September 2001	Purcell et al.
6286024	September 2001	Yano et al.
6360189	March 2002	Hinds et al.
6393555	May 2002	Meier et al.
6490607	December 2002	Oberman
6571265	May 2003	Story
6594681	July 2003	Prabhu
6629120	September 2003	Walster et al.
6658443	December 2003	Walster
6658444	December 2003	Walster et al.
6697832	February 2004	Kelley et al.
6732134	May 2004	Rosenberg et al.
6789098	September 2004	Dijkstra
2002/0194232	December 2002	Walster
2003/0033335	February 2003	Walster

Other References

US. Appl. No. 10/320,547, filed Dec. 17, 2002, Steele, Jr. cited by other .
U.S. Appl. No. 10/320,450, filed Dec. 17, 2002, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,579, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,580, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,581, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,582, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,583, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,584, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035.585, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,586, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,587, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,589, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,595, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,647, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,674, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,741, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,746, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/035,747, filed Dec. 28, 2001, Steele, Jr. cited by other .
U.S. Appl. No. 10/036,133, filed Dec. 28, 2001, Steele, Jr. cited by other .
Title: "Safe Treatment of Overflow and Underflow Conditions", by Robert A. Fraley & J. Stephen Walther, Hewlett-Packard Co., pp. 1-5. cited by other .
Title: "Vax Floating Point: A Solid Foundation for Numerical Computation", by Mary Payne & Dileep Bhandarkar, Digital Equipment Corp., pp. 1-12. cit- ed by other .
Title: Lecture Notes on the Status of "IEEE Standard 754 for Binary Floating-Point Arithmetic", by Prof. W. Kahan, May 31, 1996, pp. 1-30. cited by other .
Title: "Interval Arithmetic Specification" by Dmitri Chiriaev & G. William Walster, Draft revised May 4, 1998, pp. 1-78. cited by other .
Title: "IEEE Standard for Binary Floating-Point Arithmetic IEEE Standard 754-1985," by Standards Committee of the IEEE Computer Society, The Institute of Electrical and Electronics Engineers, Inc., copyright 1985, pp. 1-14. cited by other.

Primary Examiner: Mai; Tan V.
Attorney, Agent or Firm: Finnegan, Henderson, Farabow, Garrett & Dunner, L.L.P.

Parent Case Text

Applicant claims the right of priority based on U.S. Provisional Patent Application No. 60/293,173 filed May 25, 2001 in the name of Guy L. Steele.

Claims

What is claimed is:

1. A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand, comprising: a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand; a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand wherein the format represents a combination of at least two of a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero exact, and inexact.

2. The floating point total order comparator circuit of claim 1, further comprising: a first operand buffer coupled to the first analysis circuit, for supplying the first floating point operand to the first analysis circuit; and a second operand buffer coupled to the second analysis circuit, for supplying the second floating point operand to the second analysis circuit.

3. The floating point total order comparator circuit of claim 1, wherein the result indicating the total order comparative relationship between the first floating point operand and the second floating point operand comprises at least one of the group comprising: the first operand is less than the second operand, the first operand is greater than the second operand, and the first operand is equal to the second operand.

4. The floating point total order comparator circuit of claim 1, wherein the total order comparative relationship indicates that if the first floating point operand has the positive NaN format and the second floating point operand has the negative NaN format, and the first floating point operand contains the same value as the second floating point operand, ignoring the encoded status information in each, then the first floating point operand is greater than the second floating point operand.

5. The floating point total order comparator circuit of claim 1, wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format and the second floating point operand has the NaN format, and the two floating point operands contain the same value in a fraction field, an exponent field, and a sign bit of the respective floating point operands, then the one of the two floating point operands containing a larger value in the encoded status information in each is greater than the other of the two floating point operands.

6. A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand, comprising: a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand; a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand; wherein the format is from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact; and wherein the total order comparative relationship represents one of a group comprising: a relationship between the first floating point operand having the NaN format and the second floating point operand having the NaN format; a relationship between having first floating point operand having the NaN format and the second floating point operand not having the NaN format; and a relationship between having a first floating point operand not having the NaN format and the second floating point operand having the NaN format.

7. The floating point total order comparator circuit of claim 6 wherein the format represents one of a positive overflow (+OV) and a negative overflow (-OV).

8. The floating point total order comparator circuit of claim 6 wherein the format represents one of a positive underflow (+UN) and a negative underflow (-UN).

9. The floating point total order comparator circuit of claim 6, wherein the format represents one of a positive infinity and a negative infinity.

10. The floating point total order comparator circuit of claim 6, wherein the result is used to condition an outcome of a floating point instruction.

11. The floating point total order comparator circuit of claim 6, wherein the total order comparative relationship indicates that: the first floating point operand having the positive zero format is greater than the second floating point operand having the negative zero format.

12. A floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand, comprising: a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand; a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand; and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand, wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format and the second floating point operand has the NaN format, then the one of the two floating point operands containing a larger value in a fraction field of the two floating point operands, ignoring the encoded status information in each, is greater than the other of the two floating point operands, regardless of a respective sign bit of each floating point operand.

13. A method for comparing a first floating point operand and a second floating point operand according to a predefined total order comparative relationship, comprising: receiving the first floating point operand and the second floating point operand; determining a first floating point format of the first floating point operand from floating point status information encoded within the first floating point operand; determining a second floating point format of the second floating point operand from floating point status information encoded within the second floating point operand; and generating a result indicating the total order comparative relationship between the first floating point operand and the second floating point operand based on the first floating point format and the second floating point format, wherein the first floating point format and the second floating point format are from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact; and wherein the total order comparative relationship indicates represents one of a group comprising: a relationship between the first floating point operand having the NaN format and the second floating point operand having the NaN format; a relationship between the first floating point operand having the NaN format and the second floating point operand not having the NaN format; and a relationship between the first floating point operand not having the NaN format and the second floating point operand having the NaN format.

14. The method of claim 13, further comprising: conditioning the outcome of a floating point instruction based upon the result generated.

15. The method of claim 13, wherein the group further comprises: positive overflow (+OV) and negative overflow (-OV).

16. The method of claim 13, wherein the group further comprises: positive overflow (+UN) and negative overflow (-UN).

17. The method of claim 13, wherein the group further comprises: positive infinity and negative infinity.

18. The method of claim 13, wherein the total order comparative relationship indicates that one of the two floating point operands having the positive zero format is greater than another of the two floating point operands having the negative zero format.

19. The method of claim 13, wherein the total order comparative relationship indicates that if the first floating point operand has the positive NaN format and the second floating point operand has the negative NaN format, and the first floating point operand contains the same value as the second floating point operand, ignoring the encoded status information in each, then the first floating point operand is greater than the second floating point operand.

20. The method of claim 13, wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format and the second floating point operand has the NaN format, and the two floating point operands contain the same value in a fraction field, an exponent field, and a sign bit of the respective floating point operands, then the one of the two floating point operands containing a larger value in the encoded status information in each is greater than the other of the two floating point operands.

21. A method for comparing a first floating point operand and a second floating point operand according to a predefined total order comparative relationship, comprising: receiving the first floating point operand and the second floating point operand; determining a first floating point format of the first floating point operand from floating point status information encoded within the first floating point operand; determining a second floating point format of the second floating point operand from floating point status information encoded within the second floating point operand; and generating a result indicating the total order comparative relationship between the first floating point operand and the second floating point operand based on the first floating point format and the second floating point format, wherein the first floating point format and the second floating point format are from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact; and wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format and the second floating point operand has the NaN format, then the one of the two floating point operands containing a larger value in a fraction field of the two floating point operands, ignoring the encoded status information in each, is greater than the other of the two floating point operands, regardless of a respective sign bit of each floating point operand.

22. A computer-readable medium on which is stored a set of instructions for comparing a first floating point operand and a second floating point operand according to a predefined total order comparative relationship, which when executed perform steps comprising: receiving the first floating point operand and the second floating point operand related to a floating point instruction; determining a first floating point format of the first floating point operand from floating point status information encoded within the first floating point operand; determining a second floating point format of the second floating point operand from floating point status information encoded within the second floating point operand; and generating a result indicating the total order comparative relationship between the first floating point operand and the second floating point operand based on the first floating point format and the second floating point format, wherein the first floating point format and the second floating point format are from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact; and wherein the total order comparative relationship represents on of a group comprising: a relationship between the first floating point operand having the NaN format and the second floating point operand having the NaN format; a relationship between the first floating point operand having the NaN format and the second floating point operand not having the NaN format; and a relationship between the first floating point operand not having the NaN format and the second floating point operand having the NaN format.

23. The computer-readable medium of claim 22, further comprising: conditioning the outcome of a floating point instruction based upon the result generated.

24. The computer-readable medium of claim 22, wherein the total order comparative relationship indicates that one of the two floating point operands having the positive zero format is greater than the other of the two floating point operands having the negative zero format.

25. The computer-readable medium of claim 22, wherein the total order comparative relationship indicates that if the first floating point operand has the positive NaN format, and the second floating point operand has the negative NaN format, and the first floating point operand contains the same value as the second floating point operand, ignoring the encoded status information in each, then the first floating point operand is greater than the second floating point operand.

26. The computer-readable medium of claim 22, wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format, and the second floating point operand has the NaN format, and the two floating point operands contain the same values in a fraction field, an exponent field, and a sign bit of the respective floating point operands, then the one of the two floating point operands containing a larger value in the encoded status information in each is greater than the other of the two floating point operands.

27. A computer-readable medium on which is stored a set of instructions for comparing a first floating point operand and a second floating point operand according to a predefined total order comparative relationship, which when executed perform steps comprising: receiving the first floating point operand and the second floating point operand related to a floating point instruction determining a first floating point format of the first floating point operand from floating point status information encoded within the first floating point operand; determining a second floating point format of the second floating point operand from floating point status information encoded within the second floating point operand; and generating a result indicating the total order comparative relationship between the first floating point operand and the second floating point operand based on the first floating point format and the second floating point format, wherein the first floating point format and the second floating point format are from a group comprising: not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact; and wherein the total order comparative relationship indicates that if the first floating point operand has the NaN format, and the second floating point operand has the NaN format, then the one of the two floating point operands containing a larger value in a fraction field of the two floating point operands, ignoring the encoded status information in each, is greater than the other of the two floating point operands, regardless of a respective sign bit of each floating point operand.

Description

INCORPORATION BY REFERENCE

Related U.S. patent application Ser. No. 10/035,747, filed on even date herewith in the name of Guy L. Steele Jr. and entitled "Floating Point System That Represents Status Flag Information Floating Point Operand," assigned to the assignee of the present application, is hereby incorporated by reference.

Related U.S. patent application Ser. No. 10/035,586, filed on even date herewith in the name of Guy L. Steele Jr. and entitled "Comparator Unit For Comparing Values Of Floating point Operands," assigned to the assignee of the present publication, is hereby incorporated by reference.

FIELD OF THE INVENTION

The invention relates generally to systems and methods for performing floating point operations, and more particularly to systems and methods for comparing a pair of floating point operands and generating a result that reflects a total ordering of the values of the operands.

BACKGROUND OF THE INVENTION

Digital electronic devices, such as digital computers, calculators, and other devices, perform arithmetic calculations on values in integer, or "fixed point," format, in fractional, or "floating point" format, or both. IEEE Standard 754, (hereinafter "IEEE Std. 754" or "the Standard") published in 1985 by the Institute of Electrical and Electronic Engineers, and adopted by the American National Standards Institute (ANSI), defines several standard formats for expressing values in floating point format, and a number of aspects regarding behavior of computation in connection therewith. In accordance with IEEE Std. 754, a representation in floating point format comprises a plurality of binary digits, or "bits," having the structure: se.sub.msb . . . e.sub.lsbf.sub.msb . . . f.sub.lsb where bit "s" is a sign bit indicating whether the entire value is positive or negative, bits "e.sub.msb . . . e.sub.lsb" comprise an exponent field represent the exponent "e" in unsigned binary biased format, and bits "f.sub.msb . . . f.sub.lsb" comprise a fraction field that represents the fractional portion "f" in unsigned binary format ("msb" represents "most significant bit" and "lsb" represents "least significant bit"). The Standard defines two general formats, namely, a "single" format which comprises thirty-two bits, and a "double" format which comprises sixty-four bits. In the single format, there is one sign bit "s," eight bits "e.sub.7 . . . e.sub.0" comprising the exponent field and twenty-three bits "f.sub.22 . . . f.sub.0" comprising the fraction field. In the double format, there is one sign bit "s," eleven bits "e.sub.10 . . . e.sub.0" comprising the exponent field and fifty-two bits "f.sub.51 . . . f.sub.0" comprising the fraction field.

As indicated above, the exponent field of the floating point representation "e.sub.msb . . . e.sub.lsb" represents the exponent "E" in biased format. The biased format provides a mechanism by which the sign of the exponent is implicitly indicated. In particular, the bits "e.sub.msb . . . e.sub.lsb" represent a binary encoded value "e" such that "e=E+bias." This allows the exponent E to extend from -126 to +127 in the eight-bit "single" format and from -1022 to +1023 in the eleven-bit "double" format, and provides for relatively easy manipulation of the exponents in multiplication and division operations, in which the exponents are added and subtracted, respectively.

IEEE Std. 754 provides for several different formats with both the single and double formats, which are generally based on the bit patterns of the bits "e.sub.msb . . . e.sub.lsb" comprising the exponent field and the bits f.sub.msb . . . f.sub.lsb comprising the fraction field. As shown in prior art FIG. 4, if a number is represented such that all of the bits "e.sub.msb . . . e.sub.lsb" of the exponent field are binary one's (that is, if the bits represent a binary-encoded value of "255" in the single format or "2047" in the double format) and all of the bits f.sub.msb . . . f.sub.lsb of the fraction field are binary zeros, then the value of the number is positive infinity 310 or negative infinity 320, depending on the value of the sign bit "s." In particular, the value "v" is .nu.=(-1).sup.s.infin. where ".infin." represents the value "infinity." On the other hand, if all of the bits "e.sub.msb . . . e.sub.lsb" of the exponent field are binary one's and if the bits f.sub.msb . . . f.sub.lsb of the fraction field are not all zeros, then the value that is represented is deemed "not a number," abbreviated in the Standard by "NaN" 330.

If a number has an exponent field in which the bits "e.sub.msb . . . e.sub.lsb" are neither all binary ones nor all binary zeros (that is, if the bits represent a binary-encoded value between 1 and 254 in the single format or between 1 and 2046 in the double format), the number is said to be in a "normalized" format 360. For a number in the normalized format, the value represented by the number is .nu.=(-1).sup.s2.sup.e-bias(1. |f.sub.msb . . . f.sub.lsb), where "|" represents a concatenation operation. Effectively, in the normalized format, there is an implicit most significant digit having the value "one," so that the twenty-three digits in the fraction field of the single format, or the fifty-two digits in the fraction field of the double format, will effectively represent a value having twenty-four digits or fifty-three digits of precision, respectively, where the value is less than two, but not less than one.

On the other hand, if a number has an exponent field in which the bits "e.sub.msb . . . e.sub.lsb" are all binary zeros, representing the binary-encoded value of "zero," and a fraction field in which the bits f.sub.msb . . . f.sub.lsb are not all zero, the number is said to be in a "de-normalized" format 370. For a number in the de-normalized format, the value represented by the number is .nu.=(-1).sup.s2.sup.e-bias+1(0. |f.sub.msb . . . f.sub.lsb). It will be appreciated that the range of values of numbers that can be expressed in the de-normalized format is disjoint from the range of values of numbers that can be expressed in the normalized format, for both the single and double formats. Finally, if a number has an exponent field in which the bits "e.sub.msb . . . e.sub.lsb" are all binary zeros, representing the binary-encoded value of "zero," and a fraction field in which the bits f.sub.msb . . . f.sub.lsb are all zero, the number has the value "zero." It will be appreciated that the value "zero" may be positive zero 340 or negative zero 350, depending on the value of the sign bit.

Generally, floating point units to perform computations whose results conform to IEEE Std. 754 are designed to generate a result in response to a floating point instruction in three steps:

(a) First, an approximation calculation step in which an approximation to the absolutely accurate mathematical result (assuming that the input operands represent the specific mathematical values as described by IEEE Std. 754) is calculated. This calculation is sufficiently precise as to allow this accurate mathematical result to be summarized by a sign bit, an exponent (typically represented using more bits than are used for an exponent in the standard floating point format), and some number "N" of bits of the presumed result fraction, plus a guard bit and a sticky bit. The value of the exponent will be such that the value of the fraction generated in step (a) consists of a 1 before the binary point and a fraction after the binary point. The bits are calculated so as to obtain the same result as the following conceptual procedure (which is impossible under some circumstances to carry out in practice): calculate the mathematical result to an infinite number of bits of precision in binary scientific notation, and in such a way that there is no bit position in the significand such that all bits of lesser significance are 1-bits (this restriction avoids the ambiguity between, for example, 1.100000 . . . and 1.011111 . . . as representations of the value "one-and-one-half"); then let the N most significant bits of the infinite significand be used as the intermediate result significand, let the next bit of the infinite significand be the guard bit, and let the sticky bit be 0 if and only if ALL remaining bits of the infinite significand are 0-bits (in other words, the sticky bit is the logical OR of all remaining bits of the infinite fraction after the guard bit).

(b) Second, a rounding step, in which the guard bit, the sticky bit, perhaps the sign bit, and perhaps some of the bits of the presumed significand generated in step (a) are used to decide whether to alter the result of step (a). For the rounding modes defined by IEEE Std. 754, this is a decision as to whether to increase the magnitude of the number represented by the presumed exponent and fraction generated in step (a). Increasing the magnitude of the number is done by adding 1 to the significand in its least significant bit position, as if the significand were a binary integer. It will be appreciated that, if the significand is all 1-bits, then magnitude of the number is "increased" by changing it to a high-order 1-bit followed by all 0-bits and adding 1 to the exponent. It will be further appreciated that,

(i) if the result is a positive number, and (a) if the decision is made to increase, effectively the decision has been made to increase the value of the result, thereby rounding the result up (that is, towards positive infinity), but (b) if the decision is made not to increase, effectively the decision has been made to decrease the value of the result, thereby rounding the result down (that is, towards negative infinity); and

(ii) if the result is a negative number, and (a) if the decision is made to increase, effectively the decision has been made to decrease the value of the result, thereby rounding the result down, but (b) if the decision is made not to increase, effectively the decision has been made to increase the value of the result, thereby rounding the result up.

(c) Finally, a packaging step, in which the result is packaged into a standard floating point format. This may involve substituting a special representation, such as the representation defined for infinity or NaN if an exceptional situation (such as overflow, underflow, or an invalid operation) was detected. Alternatively, this may involve removing the leading 1-bit (if any) of the fraction, because such leading 1-bits are implicit in the standard format. As another alternative, this may involve shifting the fraction in order to construct a denormalized number. As a specific example, we assume that this is the step that forces the result to be a NaN if any input operand is a NaN. In this step, the decision is also made as to whether the result should be an infinity. It will be appreciated that, if the result is to be a NaN or infinity, any result from step (b) will be discarded and instead the appropriate representation will be provided as the result.

In addition in the packaging step, floating point status information is generated, which is stored in a floating point status register. The floating point status information generated for a particular floating point operation typically includes indications, for example, as to whether

(i) a particular operand is invalid for the operation to be performed ("invalid operation");

(ii) if the operation to be performed is division and the divisor is zero ("division-by-zero");

(iii) an overflow occurred during the operation ("overflow");

(iv) an underflow occurred during the operation ("underflow"); and

(v) the rounded result of the operation is not exact ("inexact").

These conditions are typically represented by flags that are stored in the floating point status register, separate from the floating point operand. The floating point status information can be used to dynamically control the operations taken in response to certain instructions, such as conditional branch, conditional move, and conditional trap instructions that may be in the instruction stream subsequent to the floating point instruction. Also, the floating point status information may enable processing of a trap sequence, which will interrupt the normal flow of program execution. In addition, the floating point status information may be used to affect certain ones of the functional unit control signals that control the rounding mode. IEEE Std. 754 also provides for accumulating floating point status information from, for example, results generated for a series or plurality of floating point operations.

IEEE Std. 754 has brought relative harmony and stability to floating point computation and architectural design of floating point units. Moreover, its design was based on some important principles, and rests on a sensible mathematical semantics that eases the job of programmers and numerical analysts. It also supports the implementation of interval arithmetic, which may prove to be preferable to simple scalar arithmetic for many tasks. Nevertheless, IEEE Std. 754 has some serious drawbacks, including: (i) Modes, which include the rounding mode and may also include a traps enabled/disabled mode, flags representing the floating point status information that is stored in the floating point status register, and traps that are required to implement IEEE Std. 754 introduce implicit serialization between floating point instructions, and between floating point instructions and the instructions that read and write the flags and modes. Rounding modes can introduce implicit serialization because they are typically indicated as global state, although in some microprocessor architectures, the rounding mode is encoded as part of the instruction operation code, which will alleviate this problem to that extent. This implicit serialization makes the Standard difficult to implement coherently in today's superscalar and parallel microprocessor architectures without loss of performance.

Implicit serialization occurs when programmers and designers try to avoid the problems caused if every floating point instruction uses, and can change, the same floating point status register. This can create problems if, for example, two instructions are executing in parallel in a microprocessor architectures featuring several CPUs running at once and both cause an update of the floating point status register. In such a case, the contents of the status register would likely be incorrect with respect to at least one of the instructions, because the other parallel instruction will have written over the original contents. Similar problems can occur in scalar processor architectures, in which several instructions are issued and processed at once. To solve this problem, programmers and designers make sure that floating point instructions that can affect the floating point status register are executed in serial fashion, one instruction completing before another begins.

(ii) The implicit side effects of a procedure that can change the flags or modes can make it very difficult for compilers to perform optimizations on floating point code. To be safe, compilers for most languages assume that every procedure call is an optimization barrier.

(iii) Global flags, such as those that signal certain modes, make it more difficult to do instruction scheduling where the best performance is provided by interleaving instructions of unrelated computations. Instructions from regions of code governed by different flag settings or different flag detection requirements cannot easily be interleaved when they must share a single set of global flag bits.

(iv) Traps have been difficult to integrate efficiently into architectures and programming language designs for fine-grained control of algorithmic behavior.

U.S. patent application Ser. No. 10/035,747, filed on even date herewith in the name of Guy L. Steele Jr. and entitled "Floating Point System That Represents Point Status Flag Information With A Floating Point Operand," describes a floating point unit in which floating point status information is encoded in the representations of the results generated thereby. By encoding the floating point status information relating to a floating point operation in the result that is generated for the operation, the implicit serialization required by maintaining the floating point status information separate and apart therefrom can be obviated. The floating point unit includes a plurality of functional units, including an adder unit, a multiplier unit, a divider unit, a square root unit, a maximum/minimum unit, a comparator unit and a tester unit, all of which operate under control of functional unit control signals provided by a control unit. U.S. patent application Ser. No. 10/035,586, filed on even date herewith in the name of Guy L. Steele, Jr. and entitled "Comparator Unit For Comparing Values Of Floating point Operands," describes a partial order comparator unit for use in connection with the floating point unit described in the aforementioned application that conforms to the requirements of IEEE Std. 754 that:

(i) operands having values -0 and +0 (negative zero and positive zero) are to be considered equal to each other, and

(ii) operands representing NaN values be considered "incomparable" (that is, not able to be compared) to any operands, including other NaN operands, regardless of the values represented by the bits comprising the sign, exponent, or fraction field(s) of the NaN operand(s) in the NaN format.

While these requirements are not unreasonable in the context of, for example, floating point computation, it is desirable to relax them under some circumstances, such as, for example, when floating point values are used as sort keys. In that case, it will be desirable to use a consistent total order on all possible floating point values, including -0, +0 and NaN values. The instant application is directed to a total order comparison system that can be used in the floating point unit described in that application, as well as in other conventional floating point units.

Systems and methods consistent with the principles of the present invention provide a total order comparison of operands, as the term "total order" is used in discrete mathematics. Total order refers to a relationship among a set of objects whereby for every pair of objects in the set, there is defined a relationship of "less than," "greater than," or "equal to." In a total order mathematical set, there are no "cannot compare" or "undefined" relationships. In contrast, in a partial order set, a "cannot compare" relationship may exist.

SUMMARY OF THE INVENTION

Embodiments consistent with the principles of the present invention provide new and improved systems and methods for comparing a pair of floating point operands and generating a result that reflects a total ordering of the values of the operands.

In one embodiment consistent with the principles of the present invention, a floating point total order comparator circuit for comparing a first floating point operand and a second floating point operand includes a first analysis circuit for determining a format of the first floating point operand based upon floating point status information encoded within the first floating point operand, a second analysis circuit for determining a format of the second floating point operand based upon floating point status information encoded within the second floating point operand, and a result generator circuit coupled to the analysis circuits for producing a result indicating a total order comparative relationship between the first floating point operand and the second floating point operand based on the format of the first floating point operand and the format of the second floating point operand. Each floating point operand may include a fraction field, an exponent field, and a sign bit. The result may condition the outcome of a floating point instruction. The floating point total order comparator circuit may recognize several predetermined operand formats, such as not-a-number (NaN), infinity, normalized, denormalized, invalid operation, overflow, underflow, division by zero, positive zero, negative zero, exact, and inexact.

BRIEF DESCRIPTION OF THE DRAWINGS

This invention is pointed out with particularity in the appended claims. The above and further advantages of this invention may be better understood by referring to the following description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a functional block diagram of an exemplary total order comparator unit constructed in accordance with the principles of the invention;

FIG. 2 depicts exemplary formats for representations of floating point values generated by the exemplary comparator unit depicted in FIG. 1;

FIG. 3 is a functional block diagram of a second exemplary embodiment of a total order comparator unit constructed in accordance with the principles of the invention; and

FIG. 4 depicts prior art formats for representations of floating point values.

DETAILED DESCRIPTION OF AN ILLUSTRATIVE EMBODIMENT

FIG. 1 is a functional block diagram of a total order comparator unit 10 constructed in accordance with the principles of the invention. Generally, the total order comparator unit 10 receives two floating point operands and, in response during a comparison operation, generates signals that indicate whether the value of one operand is greater than the value of the other, the value of one operand is less than the value of the other, or the values of the two operands are equal. Thus, systems and methods consistent with the principles of the present invention provide a total order comparison of operands, as the term "total order" is used in discrete mathematics. Total order refers to a relationship among a set of objects whereby for every pair of objects in the set, there is defined a relationship of "less than," "greater than," or "equal to." In a total order mathematical set, there are no "cannot compare" or "undefined" relationships. In contrast, in a partial order set, a "cannot compare" relationship may exist.

As will be described below, in some cases, operands received by the exemplary total order comparator unit 10 may include floating point status information. In those cases, the floating point status information is encoded in and comprises part of the floating point representation of the operands, as well as the generated result. Since the floating point status information comprises part of the result, instead of being separate and apart from the operands (e.g., in a status register) as in prior art comparator units, the implicit serialization that is required by maintaining the floating point status information separate and apart from the result can be obviated. The total order comparator unit 10 facilitates the comparison of values of the respective operands in a manner so as to accommodate the floating point status information that may be included therein.

The exemplary total order comparator circuit 10 encodes the floating point status information in results that are generated in certain formats. FIG. 2 depicts exemplary formats of floating point operands that the total order comparator unit 10 may receive, and of results that it may generate. With reference to FIG. 2, seven exemplary formats are depicted, including a zero format 100, an underflow format 101, a denormalized format 102, a normalized non-zero format 103, an overflow format 104, an infinity format 105 and a not-a-number (NaN) format 106. The zero format 100 is used to represent the values "zero," or, more specifically, positive or negative zero, depending on the value of "s," the sign bit.

The exemplary underflow format 101 provides a mechanism by which the floating point total order comparator circuit 10 can indicate that the result of a computation is an underflow. In the underflow format, the sign bit "s" indicates whether the result is positive or negative, the bits e.sub.msb . . . e.sub.lsb of the exponent field are all binary zeros, and the bits f.sub.msb . . . f.sub.lsb+1 of the fraction field, except for the least significant bit, are all binary zeros. The least significant bit f.sub.lsb of the fraction field is a binary one.

The exemplary denormalized format 102 and normalized non-zero format 103 are used to represent finite non-zero floating point values substantially along the lines of that described above in connection with IEEE Std. 754. In both formats 102 and 103, the sign bit "s" indicates whether the result is positive or negative. The bits e.sub.msb . . . e.sub.lsb of the exponent field of the denormalized format 102 are all binary zeros, whereas the bits e.sub.msb . . . e.sub.lsb of the exponent field of the normalized non-zero format 103 are mixed ones and zeros, except that the exponent field of the normalized non-zero format 103 will not have a pattern in which bits e.sub.msb . . . e.sub.lsb+1 are all binary ones and the least significant bit e.sub.lsb zero and all of the bits f.sub.msb . . . f.sub.lsb of the fraction field are all binary ones. In both formats 102 and 103, the bits f.sub.msb . . . f.sub.lsb of the fraction field are not all binary zeros.

The exemplary overflow format 104 provides a mechanism by which the floating point total order comparator circuit 10 can indicate that the result of a computation is an overflow. In the overflow format 104 the sign bit "s" indicates whether the result is positive or negative, the bits e.sub.msb . . . e.sub.lsb+1 of the exponent field are all binary ones, with the least significant bit e.sub.lsb being zero. The bits f.sub.msb . . . f.sub.lsb of the fraction field are all binary ones.

The exemplary infinity format 105 provides a mechanism by which the floating point total order comparator circuit 10 can indicate that the result is infinite. In the infinity format 105, the sign bit "s" indicates whether the result is positive or negative, the bits e.sub.msb . . . e.sub.lsb of the exponent field are all binary ones, and the bits f.sub.msb . . . f.sub.lsb+5 of the fraction field are all binary zeros. The five least significant bits f.sub.lsb+4 . . . f.sub.lsb of the fraction field are flags, which will be described below.

The exemplary NaN (not-a-number) format 106 provides a mechanism by which the floating point total order comparator circuit 10 can indicate that the result is not a number. In the NaN format, the sign bit "s" can be