Transposing of bits in input data to form a comparand within a content addressable memory Number:7,412,561 from the United States Patent and Trademark Office (PTO) owispatent An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.<H addressable, Transposing, Transposing, of, , 7412561.html, Patent, pto, 7412561

Title: Transposing of bits in input data to form a comparand within a content addressable memory

Abstract: An apparatus and method of transposing one or more bits in input data relative to other bits of the input data to form a compound for searching in a content addressable memory. The comparand may have one or more bits rearranged from their order appearing in the input data such that one or more bits from a first segment of the input data are replaced with, or substituted by, one or more bits from a second segment of the input data.

Patent Number: 7,412,561 Issued on 08/12/2008 to Argyres, et al.

Inventors: Argyres; Dimitri C. (San Jose, CA), Srinivasan; Varadarajan (Los Altos Hills, CA)
Assignee: NetLogic Microsystems, Inc. (Mountain View, CA)

Appl. No.: 10/801,462

Filed: March 15, 2004

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10047754	Jan., 2002	7237058

Current U.S. Class: 711/108 ; 365/49.1

Current International Class: G06F 12/00 (20060101); G11C 15/00 (20060101)

References Cited [Referenced By]

U.S. Patent Documents


3648254	March 1972	Beausoleil
4845668	July 1989	Sano et al.
4958377	September 1990	Takahashi
4996666	February 1991	Duluk, Jr.
5319762	June 1994	Mayer
5414704	May 1995	Spinney
5438535	August 1995	Lattibeaudiere
5444649	August 1995	Nemirovsky
5479112	December 1995	Choi et al.
5642322	June 1997	Yoneda
5808927	September 1998	Hesson
5860085	January 1999	Stormon et al.
5870324	February 1999	Helwig et al.
5920886	July 1999	Feldmeier
5956336	September 1999	Loschke et al.
5978885	November 1999	Clark, II
6041389	March 2000	Rao
6069573	May 2000	Clark, II et al.
6081440	June 2000	Washburn et al.
6081442	June 2000	Igarashi et al.
6098147	August 2000	Mizuhara
6121791	September 2000	Abbott
6161144	December 2000	Michels et al.
6226710	May 2001	Melchior
6243281	June 2001	Pereira
6324087	November 2001	Pereira
6351142	February 2002	Abbott
6353873	March 2002	Melchior
6374326	April 2002	Kansal et al.
6424659	July 2002	Viswanadham et al.
6629099	September 2003	Cheng
6633953	October 2003	Stark
2002/0015348	February 2002	Gillingham
2002/0126672	September 2002	Chow et al.
2003/0005146	January 2003	Miller et al.
2003/0039135	February 2003	Srinivasan et al.
2003/0084236	May 2003	Khanna et al.
2004/0128434	July 2004	Sandeep et al.

Primary Examiner: Portka; Gary J
Attorney, Agent or Firm: Shemwell Mahamedi LLP

Parent Case Text

REFERENCE TO RELATED APPLICATION

This application is a continuation-in-part of U.S. application Ser. No. 10/047,754 filed Jan. 14, 2002, now U.S. Pat. No. 7,237,058 hereby incorporated by reference.

Claims

What is claimed is:

1. An apparatus, comprising: control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising B, A B, and AB; and switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations; wherein the control logic is coupled to receive a first plurality of enable signals, each of the first plurality of enable signals corresponding to a first plurality of one or more bits of a first segment of the input data, and wherein the control logic is coupled to receive a second plurality of enable signals, each of the second plurality of enable signals corresponding to a second plurality of one or more bits of a second segment of the input data.

2. The apparatus of claim 1, wherein the plurality of logic cells are coupled in a matrix of N columns and M rows comprising: a first row of logic cells, each of the logic cells in the first row having first inputs to receive a corresponding one of the first plurality of enable signals, wherein a first one of the logic cells in the first row has an input coupled to receive a first one of the second plurality of enable signals, wherein N-1 number of succeeding logic cells in the first row have second inputs coupled to receive the result of the B logic operation of a preceding logic cell in the first row as the B operand; and a first column of logic cells, each of the logic cells in the first column having first inputs to receive a corresponding one of the second plurality of enable signals, wherein a first one of the logic cells in the first column has an input coupled to receive a first one of the first plurality of enable signals, wherein M-l number of succeeding logic cells in the first column have second inputs coupled to receive the result of the A Blogic operation of a preceding logic cell in the first column as the A operand, wherein each of the logic cells in the first column provides the result of the AB logic operation.

3. The apparatus of claim 2, wherein the switch circuitry further comprises: a first plurality of multiplexers, each of the first plurality of multiplexers coupled to receive the result of the AB logic operation of the first and second columns of logic cells as control inputs, wherein each of the first plurality of multiplexers is coupled to receive the second plurality of one or more bits of the second segment of the input data, each of the first plurality of multiplexers to selectively output one of the second plurality of one or more bits of the second segment based on the result of the AB logic operation of the first and second columns of logic cells.

4. The apparatus of claim 3, wherein the switch circuitry further comprises: a second plurality of multiplexers, each of the second plurality of multiplexers coupled to receive a corresponding one of the first enable signals as a control input, wherein each of the plurality of second multiplexers is coupled to receive a corresponding one of the first plurality of one or more bits of the first segment as a first input and the selected output of a corresponding one of the first plurality of multiplexers as a second input, each of the second plurality of multiplexers to selectively output one of the first and second inputs based on the control input.

5. The apparatus of claim 1, wherein the at least one of the plurality of logic cells has a first input, a second input, a first output, a second output and a third output, and wherein the first input is coupled to receive a first one of the plurality of first enable signals as the A operand, wherein the second input is coupled to receive a first one of the plurality of second enable signals as the B operand, wherein the first output provides the result of the B logic operation, wherein the second output provides the result of the A Blogic operation, and wherein the third output provides the result of the AB logic operation.

6. The apparatus of claim 5, wherein the plurality of logic cells comprises: a first logic cell comprising the at least one of the plurality of logic cells; a second logic cell, the second input of the second logic cell coupled to receive the result of the B logic operation from the first logic cell as the B operand of the second logic cell, the first input of the second logic cell coupled to receive a second one of the plurality of first enable signals as the A operand of the second logic cell, the third output of the second logic cell to provide the result of the AB logic operation of the second logic cell; a third logic cell, the second input of the third logic cell coupled to receive a second one of the plurality of second enable signals as the B operand of the third logic cell, the first input of the third logic cell coupled to receive the result of the A Blogic operation of the first logic cell as the A operand of the third logic cell, the third output of the third logic cell to provide the result of the AB logic operation of the third logic cell; and a fourth logic cell, the second input of the fourth logic cell coupled to receive the result of the B logic operation from the third logic cell as the B operand of the fourth logic cell, the first input of the fourth logic cell coupled to receive the result of the A Blogic operation of the second logic cell as the A operand of the fourth logic cell, the third output of the fourth logic to provide the result of the AB logic operation of the fourth logic cell.

7. The apparatus of claim 6, wherein the switch circuitry comprises: a first multiplexer having control inputs coupled to receive the result of the AB logic operation from the first and third logic cells, the first multiplexer having inputs coupled to receive the first plurality of one or more bits of the second segment of the input data, the first multiplexer to selectively output one of the first plurality of one or more bits of the second segment of the input data based on the result of the AB logic operation from the first and second logic cells; and a second multiplexer having control inputs coupled to receive the result of the AB logic operation from the fourth and second logic cells, the second multiplexer having inputs coupled to receive the first plurality of one or more bits of the second segment of the input data, the second multiplexer to selectively output one of the first plurality of one or more bits of the second segment of the input data based on the result of the AB logic operation from the first and second logic cells.

8. The apparatus of claim 7, wherein the switch circuitry further comprises: a third multiplexer having a control input coupled to receive the first one of the plurality of first enable signals, the third multiplexer having a first input coupled to receive one of the first plurality of one or more bits of the first segment of input data, the third multiplexer having a second input coupled to receive the output of the first multiplexer, the third multiplexer to selectively output either the one of the first plurality of one or more bits of the first segment of input data or the output of the first multiplexer based on the first one of the plurality of first enable signals; and a fourth multiplexer having a control input coupled to receive the second one of the plurality of first enable signals, the fourth multiplexer having a first input coupled to receive another of the first plurality of one or more bits of the first segment of input data, the fourth multiplexer having a second input coupled to receive the output of the second multiplexer, the fourth multiplexer to selectively output either the another of the first plurality of one or more bits of the first segment of input data or the output of the second multiplexer based on the second one of the plurality of first enable signals.

9. The apparatus of claim 2, wherein the control logic comprises matrix of N columns and M rows of logic cells, where N is equal to a number of the first plurality of enable signals and M is equal to a number of the second plurality of enable signals.

10. An apparatus, comprising: control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising B. A B, and AB; and switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations; a content addressable memory (CAM) array coupled to receive a comparand; and a filter circuit coupled to the CAM array, the filter circuit comprising the switch circuitry and the control logic, wherein the filter circuit is coupled to receive the input data and transpose the one or more bits of the input data from an initial position in the input data to a different position in the comparand relative to other bits of the input data that are transposed to the comparand.

11. The apparatus of claim 10, wherein the input data segment and a second data segment and wherein the filter circuit is configured to replace one or more bits of the first data segment with one or more bits from the second data segment to form the comparand.

12. The apparatus of claim 11, further comprising a comparand register coupled between the CAM array and the filter circuit to store the comparand.

13. An apparatus, comprising: control logic comprising a plurality of logic cells, at least one of the plurality of logic cells configured to receive an A operand and a B operand and perform the following logic operations comprising B, A B, and AB; and switch circuitry coupled to receive input data, the switch circuitry coupled to the control logic to receive a result of the AB logic operation from each of the plurality of logic cells and selectively enable the output of one or more bits of the input data based on the results of the AB logic operations; wherein at least another of the plurality of logic cells is configured to receive a result of the B logic operation of the at least one logic cell and an enable signal as the B operand, and wherein the at least another of the plurality of logic cells is configured to perform the AB logic operation.

14. A method, comprising: providing a matrix of M rows and N columns of logic cells in a content addressable memory (CAM) device, where N is equal to or greater than 1 and M is greater than 1; performing an AB logic operation in each of the logic cells; selecting among a second one or more bits of input data using a result of the AB logic operation in at least one of the logic cells; and selecting between the selected second one or more bits of input data and a first one or more bits of input data for output to a comparand in the CAM device.

15. The method of claim 14, further comprising: receiving a first enable signal as an A operand in a first one of the logic cells, the first enable signal corresponding to the first one or more bits of input data; and receiving a second enable signal as a B operand in the first one of the logic cells, the second enable signal corresponding to the second one or more bits of input data.

16. The method of claim 15, further comprising: performing an B logic operation in the first logic cell and providing a result of the B logic operation as a B operand to a second logic cell; and performing an A Blogic operation in the first logic cell and providing a result of the A Blogic operation as an A operand to a third logic cell.

17. The method of claim 16, wherein performing the AB logic operation in at least one of the logic cells comprises: performing the AB logic operation in the first logic cell to generate a first result; and performing the AB logic operation in the second logic cell to generate a second result.

18. The method of claim 17, wherein selecting among the second one or more bits of input data using the result of the AB logic operation comprises using at least one of the first and second results to select among the second one or more bits of input data.

19. The method of claim 18, wherein selecting between the selected second one or more bits of input data and the first one or more bits of input data for output to the comparand comprises using the received first enable signal.

20. The method of claim 15, wherein performing the AB logic operation in each of the logic cells comprises: performing the AB logic operation in each of a N number of logic cells in the first row of the matrix of logic cells using the A operand; and performing the AB logic operation in each of a M number of logic cells in a first column of the matrix of logic cells using the B operand.

21. The method of claim 20, wherein performing the AB logic operation in each of the logic cells further comprises: performing the following logic operations in each of an M-1 number of logic cells in each of the M rows and each of an N-1 number of logic cells in each of the N columns: an B logic operation and an A Blogic operation; receiving a result of the B logic operation of a preceding logic cell in a row of the M rows as the Boperand in a succeeding cell in the row and performing the AB logic operation in the N-1 number of succeeding logic cells in the row; and receiving a result of the A Blogic operation of a preceding logic cell in a column of the N columns as the A operand in a succeeding cell in the column and performing the AB logic operations in the M-1 number of succeeding logic cells in the column.

22. A content addressable memory (CAM) device, comprising: a matrix of M rows and N columns of logic cells, where N is equal to or greater than 1 and M is greater than 1; means for performing an AB logic operation in each of the logic cells; means for selecting among a second one or more bits of input data using a result of the AB logic operation in at least one of the logic cells; and means for selecting between the selected second one or more bits of input data and a first one or more bits of input data for output to a comparand in the CAM device.

Description

TECHNICAL FIELD

This invention relates generally to the field of memory devices. More specifically, the invention relates to content addressable memory devices.

BACKGROUND

Networks contain a collection of computing systems (e.g., clients and servers) that are interconnected by transmission lines to enable the transfer of data between them. A network typically includes multiple access points (e.g., routers and servers) that may switch and/or route data between transmission lines to transfer data from a source to a destination. Data is typically transmitted in the form of packets that are made up of smaller data cells. A packet is a unit of data that is routed between a source and a destination on a packet-switched network. When a file (e.g., e-mail, graphics, etc.) is sent from one place to another on a network, the file is divided into such smaller packets making them more efficient for transmission. The individual packets for a given file may travel different routes throughout networks with each packet containing both data and transmission information associated with the routing of data. As such, a packet may be described as having a payload containing the data, and one or more headers that contain the routing information (e.g., a destination address).

When all the packets have arrived at a destination, they are reassembled into the original file at the receiving end. Such a packet switching scheme is an efficient way to handle transmission on a connectionless network. This is in contrast to a circuit switching scheme where a connection (e.g., a voice connection) requires the dedication of a particular path for the duration of the connection.

A router is a device (e.g., hardware, firmware, software) that determines the next network segment to which a packet should be forwarded towards its destination. A router may be positioned at points within a network or where one network meets another, referred to as a gateway. A router may create and maintain tables of the available routes and their conditions for use with other information to determine the best route for a given packet. Typically, a packet may travel through a number of network points having routers before arriving at its destination.

When a data packet arrives at the input of a router, several lookups may be performed to determine the subsequent handling of the packet, as illustrated in FIG. 1. The lookups may include, for examples, where to send the packet next (Next Hop), the quality of service requirement (QoS), the Ethernet port address, etc. Consider, for example, a packet arriving at Router-A. Router-A needs to determine whether the packet is destined for local servers connected directly to Router-A, or if the packet should go to the next router on a route (Router-B) to a destination. Additionally, Router-A may assign a priority based on the destination address (DA) and the source address (SA) of the packet.

The packet header may first be processed to get the values from different fields (e.g., SA, DA, protocol type, QoS, etc) in order to perform the various lookups. A packet classification lookup, for example, may be performed using SA, DA and other relevant fields in the packet header. The Next Hop lookup, for example, may also be performed to determine whether the packet is meant for local servers or for Router-B. If the packet is destined for Router-B, the packet is then put in a queue for Router-B. If the packet is destined for a local server (e.g., Server-1 or Server-2), then a media access control (MAC) lookup is performed to send the packet to the appropriate server. In the preceding example, three lookups are necessary for sending the packet on its way: Packet Classification, Next Hop, and MAC. However, often there are other lookups performed on the packet header.

Routers may use processors and content addressable memory (CAM) devices to perform the various lookups on packets. A CAM device can be instructed by a processor to compare a search key, also referred to as comparand data (e.g., packet header data), with data stored in its associative memory array, as illustrated in FIG. 2. The CAM simultaneously examines all of its entries and selects the stored data that matches the comparand.

When the entire CAM device is searched simultaneously for a match of the stored data with the comparand data, the CAM device indicates the existence of a match by asserting a match flag. Multiple matches may also be indicated by asserting a multiple match flag. The CAM device typically includes a priority encoder to translate the matched location into a match address or CAM index and outputs this address to a status register so that the matched data may be accessed. The priority encoder may also sort out which matching memory location has the top priority if there is more than one matching entry.

A router may include multiple CAMs, with each CAM having a different table or, alternatively, a single CAM having multiple blocks for each of the different tables, for performing the different lookups. For example, a router may include a 32 bit wide Next Hop CAM, a 128 bit Classification CAM, and a 48 bit MAC CAM. With routers having multiple CAMs, each of the multiple CAMs are typically connected to common buses that are used to communicate the various keys and other input and output data with each of the CAM device, With such a configuration common input data may be provided to the multiple CAM device, or multiple blocks of single CAM device. However, different CAM devices, or different blocks within a multiblock CAM device, may require different portions of the input data to use the comparand for performing a look-up in a particular table.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention is illustrated by way of example and not intended to be limited by the figures of the accompanying drawings.

FIG. 1 illustrates an example of packet handling by a router.

FIG. 2 illustrates one embodiment of a conventional CAM device.

FIG. 3 illustrates one embodiment of a line card or blade of a router having a CAM device configured according to one embodiment of the present invention.

FIG. 4 illustrates one embodiment of a lookup string.

FIG. 5 illustrates one embodiment of a CAM device having a filter circuit.

FIG. 6 is a conceptual illustration of an exemplary embodiment of bit transposition.

FIG. 7 illustrates one embodiment of the filter circuit of FIG. 5.

FIG. 8 illustrates one embodiment of the control logic of FIG. 7.

FIG. 9 illustrates one embodiment of the switch circuitry of FIG. 7.

FIG. 10A illustrates one example of the operation of the control logic of FIG. 8.

FIG. 10B illustrates one example of the switch circuitry of FIG. 9.

FIG. 11 illustrates one embodiment of a method of bit transposition in input data.

FIG. 12 illustrates another embodiment of a CAM device having multiple CAM blocks.

DETAILED DESCRIPTION

In the following description, numerous specific details are set forth such as examples of specific components, circuits, processes, etc. in order to provide a thorough understanding of the present invention. It will be apparent, however, to one skilled in the art that these specific details need not be employed to practice the present invention. In other instances, well known components or methods have not been described in detail in order to avoid unnecessarily obscuring the present invention.

Embodiments of the present invention include various methods, which will be described below. The methods may be performed by hardware components or may be embodied in machine-executable instructions, which may be used to cause hardware components (e.g., a processor, programming circuit) programmed with the instructions to perform the methods. Alternatively, the methods may be performed by a combination of hardware and software.

Embodiments of the present invention may be provided as a computer program product, or software, that may include a machine-readable medium having stored thereon instructions. The machine readable medium may be used to program a computer system (or other electronic devices) to generate articles (e.g., wafer masks) used to manufacture embodiments of the present invention. The machine-readable medium may include, but is not limited to, floppy diskettes, optical disks, CD-ROMs, and magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, magnet or optical cards, flash memory, or other type of media/machine-readable medium suitable for storing electronic instructions.

The machine readable medium may store data representing an integrated circuit design layout that includes embodiments of the present invention. The design layout for the integrated circuit die may be generated using various means, for examples, schematics, text files, gate-level netlists, hardware description languages, layout files, etc. The design layout may be converted into mask layers for fabrication of wafers containing one or more integrated circuit dies. The integrated circuit dies may then be assembled into packaged components. Design layout, mask layer generation, and the fabrication and packaging of integrated circuit dies are known in the art; accordingly, a detailed discussion is not provided.

It should be noted that the steps and operations discussed herein (e.g., the loading of registers) may be performed either synchronously or asynchronously. The term "coupled" as used herein means connected directly to or connected through one or more intervening components or circuits. Any of the signals provided over various buses described herein may be time multiplexed with other signals and provided over one or more common buses. Additionally, the interconnection between circuit elements or blocks may be shown as buses or as single signal lines. Each of the buses may alternatively be single signal lines, and each of the single signal lines may alternatively be buses. Additionally, the prefix symbol "/" the suffix "B" attached to signal names indicates that the signal is an active low signal. Each of the active low signals may be changed to active high signals as generally known in the art. A line over an operand such as " " means the logical compliment of the operand.

The methods and apparatus described herein may be used to transpose one or more bits (or groups of bits such as a byte) in an input data relative to other bits in the input data to form a comparand for searching in a content addressable memory. The comparand may have one or more bits (or group of bits) rearranged from their order appearing in the input data such that one or more bits (or group of bits) from a first segment of the input data are replaced with, or substituted by, one or more bits (or group of bits) from a second segment of the input data. The one or more bits from the first segment of input data that form the comparand maintain the same order in the comparand as their order in the first segment of input data. The replacement one or more bits (from the second segment) occupy the positions in the comparand as the replaced one or more. bits (from the first segment) would have occupied in the comparand had they been used to form the comparand.

The apparatus includes a filter circuit that transposes the input data, according to the needs of the user. The filter circuit includes switch circuitry (e.g., a cross-bar switch, switch matrix, switch fabric, etc.) and control logic. The control logic selects or enables particular switch paths of the switch circuit to provide one or more bits (or groups of bits) from the input data to particular positions in the comparand.

FIG. 3 illustrates one embodiment of a line card or blade of a router having a CAM device. Line card 300 includes processor 310, ingress interface circuitry 330, egress interface circuitry 340, CAM device 320, associated data storage unit 370, traffic manager 360, and payload storage unit 350.

Processor 310 functions to control the overall operation of line card 300 in cooperation with the other components of line card 300. For example, processor 310 receives packets from a network medium through ingress interface circuitry 330, stores the payload of packets in payload storage unit 350, and processes packet header information to determine required lookups in CAM device 320 and subsequent handling of the packets, as discussed herein. Ingress circuitry includes, for example, physical layer (PHY) and MAC devices. Processor 310 sends out packets on a network medium through egress interface circuitry 340 based on the lookups performed by CAM device 320. Egress interface circuitry 340 may be connected to a switch fabric or directly to one or more other routers or switches. Processor 310 may be one or more network processor units (NPUs), microprocessors, or one or more special purpose processors such as a digital signal processor (DSP). In another embodiment, processor 310 may be another type of controller, for example, a field programmable gate array or a general purpose processor. The processor 310, ingress interface circuitry 330, and egress interface circuitry 340 components of a router are known in the art; accordingly, a detailed discussion is not provided.

In response to information in a packet header, for a particular packet, processor 310 determines the number and types of lookups to be performed by one or more of CAM devices 320, and forms the search keys for these lookups. The searches or lookups may include, for example, classification lookups, forwarding lookups (e.g., Next Hop or longest prefix match (LPM) lookup, MAC lookup, MPLS lookup, etc.). When multiple searches are required, processor 310 forms a composite search key that includes at least two, and as many as all, of the various search keys for the lookups. The composite search key is provided as a common input data to CAM device 320. CAM device 320 selectively identifies and extracts the individual search keys from the common input data and provides the individual search keys to the associated CAM blocks to perform the lookups. Advantageously, the lookups can then occur concurrently or simultaneously in the CAM blocks of CAM device 320, thereby increasing overall throughput over conventional systems in which searches are processed sequentially.

CAM device 320 may be a multiple block CAM device with each block having a corresponding filter circuit, as discussed below, to generate a comparand for a lookup. Alternatively, CAM device 320 may represent multiple, single block CAM devices (e.g., with each single block CAM device formed on a different integrated circuit substrate) with each CAM device having a corresponding filter circuit. After one or more lookups are executed in CAM device 320, associated information for matching entries (e.g., additional routing information and/or packet information) may be retrieved from associated data unit 370. Processor 310 then communicates with traffic manager 360 to schedule the exit of a packet from line card 300 via egress interface circuitry 340.

FIG. 4 illustrates one embodiment of an input data string. Input data 400 includes field segments processed (e.g., separated) from one or more packet headers 402 and 404. When data processing systems (e.g., routers, clients, servers) exchange data over a network, the procedure involves the use of protocols by which these systems agree on how to communicate with each other. To reduce design complexity, networks may be organized as a series of layers. The number of layers and the function of each layer varies from network to network.

For example, where a transmission control protocol (TCP)/Internet protocol (IP) is used, it is organized into multiple layers including a network access layer and an Internet layer. The network access layer uses a TCP to enable the exchange of data between an end system and a network. An Internet layer uses an IP to enable data to transverse multiple interconnected networks. Each of these protocols uses packet headers containing routing information, as discussed above. For example, TCP packet header 402 includes a source address (SA) port segment 406 and a destination address (DA) port segment 408, and IP packet header 404 includes a SA segment 410, a DA segment 412, a type of service (ToS) segment 414, and a protocol type segment 416.

In one embodiment, for example, processor 310 of FIG. 3 may be used to process certain segments from packet headers 402 and 404 to generate input data 400 and transmit the input data to CAM device 320. For example, input data 400 may include MAC segment 418, TOS segment 414, SA port segment 406, DA port segment 408, SA segment 410, and DA segment 412. Alternatively, input data 400 may include more or less than the segments illustrated. A filter circuit (illustrated in FIG. 5) may then filter out the bit values of different field segments of input data 400 to generate a filtered comparand to perform a lookup in a CAM array. In an alternative embodiment, processor 310 may transmit as-received unprocessed header segments to CAM device 320.

FIG. 5 illustrates CAM device 500 that is, for example, one embodiment of CAM device 320 of FIG. 3. CAM device 500 includes address circuit 512, instruction decoder 510, CAM array 502, read/write (R/W) circuitry 514, priority encoder 516, match flag logic 518, comparand register 504 and filter circuit 506. Additional circuits such as, for example, error detection logic, multiple match flag logic, full flag logic, almost full flag logic, etc. may also be used. Alternatively, the flag logic may be omitted.

Instruction decoder 510 decodes various instructions provided on instruction bus IBUS (e.g., instructions to write or read data from CAM array 502 and to compare comparand data with one or more segments of the CAM array) and provides various control and/or timing signals to address circuit 512, filter circuit 506, R/W circuitry 514, and comparand register 504, to control when CAM device 500 performs an operation (e.g., a read, write or compare operation). Instruction decoder 510 may also provide various control and/or timing signals to CAM array 502, priority encoder 516 and match flag logic 518. The instruction decoder 510 may be, for example, a look-up table, state machine or other control logic. In an alternate embodiment, instruction decoder 510 is omitted and various read, write and compare control signals are provided directly to one or more of the circuit blocks.

In one embodiment, input data 508 includes N+M bits, where M is the number of bits (or group of bits) in a second data segment 532 of input data 508 is the number of bits (or group of bits) in a first data segment of input data 508, where M and N are each greater than or equal to one. Input data 508 may be generated by, for example, processor 310 of FIG. 300.

Filter circuit 506 receives input data 508 and control information 507 that is used to program filter circuit 506 to generate a particular comparand from input data 508. The control information 507 may be received from instruction decoder 510 or, alternatively, from other components such as directly from processor 310 of FIG. 300. In one embodiment, filter circuit 506 includes switch circuitry (e.g., a cross-bar switch, switch matrix, switch fabric, etc.) and control logic, as discussed below in relation to FIG. 7. Filter circuit 506 transposes one or more bits (or group of bits) from their position(s) in input data 508 to their position(s) in comparand 509 based on the control information 507.

In one embodiment, CAM array 502 is coupled to comparand register 504 that receives a comparand 509 from filter circuit 506 for comparison with data stored in one or more CAM cells of CAM array 502. During a compare operation, CAM array 502 is searched for a match with comparand 509. The comparand 509 may be stored in a comparand storage element, for example, comparand register 504 before a compare operation (look-up) in CAM array 502 is performed. Alternatively, the comparand 509 may be provided directly to CAM array 602 through comparand drivers (not shown) without being stored in comparand register 504. The CAM device 500 may also include one or more global mask registers (not shown) to mask certain portions of comparand 509 provided to CAM array 502.

CAM array 502 is an array of CAM cells that includes any number of rows of CAM cells that may be any type of CAM cells including, for example, binary and ternary NAND and NOR based cells that may be formed from either volatile or non-volatile elements. Each CAM cell includes at least one memory storage element and at least one compare circuit. Other embodiments may be used to effectively implement an array of CAM cells.

Data to be written to CAM array 502 may be received from DBUS. The data is written to CAM array 502 by read/write circuitry 514 and address logic 512. Address logic 512 selects one or more rows of CAM cells in response to an address provided over ADDR. The write data is provided to the selected cells (e.g., over one or more data bit lines) by the write circuitry portion of read/write circuitry 514 (e.g., write buffers). The read circuitry portion of read/write circuitry 654 (e.g., sense amplifiers) enables data to be read from one or more selected rows of CAM array 502. The data read from CAM array 502 may be output from the read/write circuitry 514 on the DBUS or any other bus (e.g., CBUS).

When CAM array 502 is searched for a match of the stored data with the comparand 509, each matching location indicates a match on one of match lines 503. Match flag logic 518 indicates the existence of a match if at least one of the match lines 503 carries a match signal indicating a match. Additional flag logic such as almost full flag logic, full flag logic, and/or multiple match flag logic may also be included in CAM device 500.

Priority encoder 516 translates a matched location(s) into an index (or a match address) and outputs this index that may be used, for example, by processor 310 of FIG. 3 or to access associated data unit 370 of FIG. 3. Priority encoder 516 also identifies which matching location has the top priority if there is more than one matching entry.

Any of the signals provided over IBUS, DBUS, CBUS or ADDR may be time multiplexed with other signals and provided over one or more of the other buses. The buses may be coupled to processor 310 as represented by bus 325 of FIG. 3. In an alternative embodiment, CAM device 500 may include multiple CAM arrays 502 (and corresponding filter circuits 506) each forming a block as discussed below in relation to FIG. 12. A block may be an entire array, a portion of a larger array, or include multiple arrays. Each array in a block may store a different lookup table or portions of one or more common lookup tables. Alternatively, a block may store multiple lookup tables. Multiple block CAM devices are known in the art; accordingly, a more detailed discussion is not provided.

FIG. 6 conceptually illustrates an exemplary embodiment of bit transposition. Each of the units/positions of the input data, control information and comparand may be discussed herein as a referring to a bit only for ease of discussion. It should be noted that, each unit/position might represent a group of bits having one or more bits within the group (e.g., a byte).

In one embodiment, input data 508 includes a first segment of data (segment one data) 531 and a second segment of data (segment two data) 532. There may be a one-to-one correspondence between the bit positions of segment one data 531 and the bit positions of comparand 509, without bit transposition, such that, for example, bit SO.sub.1, of input data 508 is used to form bit C.sub.1 and bit S0.sub.8 is used to form bit C.sub.8 of comparand 509. Filter circuit 506 is used to transpose bits, based on control information 507, of the segment two data 532 to particular bit positions in the comparand 509 that might have otherwise been occupied by bits of the segment one data 531 without such transposition. In the particular, bits from segment one data 531 may be replaced by, or substituted with, bits from segment two data 532 in forming the comparand 509. The bits from the segment one data 531 that are used to form the comparand maintain the same order in the comparand 509 as their order in the segment one data 531 of input data 508. The replacement bits (from the segment two data 532) occupy the same positions in the comparand 509 as the replaced bits (from the segment one data) would have occupied in the comparand had the replaced bits been used to form the comparand 509.

For the exemplary embodiment shown in FIG. 6, bits SO.sub.1, SO.sub.2 and SO.sub.7 of segment one data 531 (that might otherwise have formed bits C.sub.1, C.sub.2 and C.sub.7 of comparand 509 without transposition) are replaced with bits ST.sub.1, ST.sub.2 and ST.sub.4 of the segment two data 532 to form comparand 509 based on the bit values of control information 507. In this exemplary embodiment, a "1" bit value in the segment one enable 541 bit positions of control information 507 is used to indicate that a corresponding segment one data 531 bit is to be used to form comparand 509, while a "1" bit value in the segment two enable 542 bit positions is used to indicate that a corresponding bit of segment two data 532 is to be used as a substitution (in order of their position in the segment two data string starting from ST.sub.1to ST.sub.4) to form comparand 509. In an alternative embodiment, the substitution queue of segment two data 532 may start from its other end (e.g., ST.sub.4).

As such, the "0"s in segment one enable 541 bit positions SO_E.sub.3 to SO_E.sub.6, and SO_E.sub.8 indicate that corresponding segment one data 531 bits S0.sub.3 to S0.sub.6 and S0.sub.8 are to be used to form comparand 509 in corresponding bit positions C.sub.3 to C.sub.6 and C.sub.8. The "1"s in segment one enable 541 bit positions SO_E.sub.1, SO_E.sub.2, and SO_E.sub.7 indicate that corresponding segment one data 531 bits S0.sub.1, S0.sub.2 and S0.sub.7 are to be replaced by bits from segment two data 532. The particular bit of segment two data 532 that is to be used to replace a particular bit of segment one data 531 in forming comparand 509 is determined by the "1" bit values in segment two enable 542. The "1" segment two enable 542 bit positions ST_E.sub.1, ST_E.sub.2 and ST_E.sub.4 indicate that the bits in corresponding segment two data 532, ST.sub.1, ST.sub.2 and ST.sub.4 are to be used (in their order within segment two data 532 starting with ST.sub.1) to form comparand 509 in comparand positions C.sub.1, C.sub.2 and C.sub.7, respectively. In alternative embodiment, a "0" rather than a "1" bit value may be used to indicate a selection.

Filter circuit 506 of FIG. 7 is used to transpose the bits ST.sub.1, ST.sub.2 and ST.sub.4 of the segment two data 532 to form bits C.sub.1, C.sub.2 and C.sub.7, respectively, of the comparand 509. While filter circuit 506 selects bits SO.sub.3, SO.sub.4, SO.sub.5, SO.sub.6, and SO.sub.8 of segment one data 531 to form bits C.sub.3, C.sub.4, C.sub.5, C.sub.6, and C.sub.8 of comparand 509, respectively, maintaining their positional correspondence in comparand 509 with respect to segment one data 531 in input data 508.

FIG. 7 illustrates one embodiment of the filter circuit of FIG. 5. In this embodiment, filter circuit 506 includes switch circuitry 750 and control logic 710. Filter circuit 506 transposes one or more bits (or group of bits) from input data 508 to certain positions in comparand 509 (e.g., that, in one embodiment, may be stored in a comparand register 504) based on the control information 507. The control information 507 enables particular switch paths of the switch circuitry to provide the one or more bits from segment two data 532 of input data 508 to particular positions in the comparand 509 in substitute of one or more bits from segment one data 531. Switch circuitry 750 includes a plurality of switch circuits, or paths (as discussed below in relation to FIGS. 9 and 10B), which are controlled by control logic 710 to connect the bits of input data 508 with particular positions in comparand 509.

FIG. 8 illustrates one embodiment of the control logic of FIG. 7. Control logic 710 includes a plurality of logic cells 840 that are coupled in a matrix of N columns and M rows, where N is equal to or greater than 1 and M is equal to or greater than 2. Each of the N columns corresponds to one of the segment one enable signals 541 and each of the M rows corresponds to one of the segment two enable signals 542 of control information 541. Each of the plurality of logic cells 840 has two inputs coupled to receive an A operand and a B operand. The logic cells perform logic operations whose results may be output to succeeding logic cells in the matrix as the A operand and/or B operand of a succeeding logic cell. Each of the logic cells performs at least an AB logic operation equaling variable Z that is output from control logic 710. The outputted results of the AB logic operations (the Zs) are used as control signals that are input to switch circuitry 750 to enable particular switch paths (e.g., a particular output of a multiplexer), as discussed below in relation to FIG. 9.

The control logic 710 includes a matrix of N by M logic cells 840.sub.NM to 840.sub.11, where N and M are greater than or equal to 1. Each logic cell is configured to receive an A operand and a B operand, and perform the following logic operations: B, A B, and AB. AB means a logic AND operation performed on operands A and B. B means a logic AND operation performed on operands and B, where is the logical complement of operand A. A B means a logic AND operation performed on operands A and B, where B is the logical complement of operand B. The results of the logic operations: B, A B, and AB are represented by the variables X, Y and Z, respectively.

Each of the logic cells in column N of the control logic 710 matrix are coupled to receive a segment two enable signal 542 as a B operand. Each of the cells in row M of the control logic 710 matrix are coupled to receive a segment one enable 541 signal as the A operand. Each of the logic cells in column N (except, in one embodiment, the logic cell in the last row 1) performs an A B logic operation and outputs the result Y as an A operand to corresponding column N logic cell in rows M-1 to 1. Each of the logic cells also performs a B logic operation and outputs the result X as a B operand to corresponding logic cell in column N-1. Each of the logic cells in column N also performs an AB logic operation and outputs the result Z. The Z outputs from each of the logic cells in a column forms column logic outputs 841.sub.1 to 841.sub.N from control logic 710, with column N logic outputs 841.sub.N corresponding to outputs Z.sub.NM to Z.sub.N1 of logic cells 840.sub.NM to 840.sub.N1 and column one logic outputs 841.sub.1 corresponding to the outputs Z.sub.1M to Z.sub.11 of logic cells 840.sub.1M to 840.sub.11. The column one logic outputs 841.sub.1 to column N logic outputs 841.sub.N are supplied as control signals to switch circuitry 750 to effectively enable one of the segment two data bits.

Each logic cell in columns N-1 to 1 receives at its B input the X output result from an immediately preceding logic cell N to 2, respectively, in its same row. Additionally, each logic cell in rows M-1 to 1 receives at its A input the Y output result from an immediately preceding logic cell M to 2, respectively, in its same column.

It should be noted that the logic cells (e.g., logic cell NM) in the last row M need not, but may, perform the A B logic operation because there are no further rows of logic cells to receive the Y result. It should also be noted that the logic cells (e.g., logic cell 840.sub.11) in the last column 1 need not, but may, perform the B logic operation because there are no further columns of logic cells to receive the X result.

In one embodiment, the logic cells 840 may be implemented with static or dynamic AND/OR gates. In one embodiment, logic cell 840 may implemented with a differential cascode voltage switch (DCVS) circuit. Alternatively, other types of circuits may be used to implement a logic cell 840, for example, static CMOS NAND and/or NOR gates. Such circuits are known in the art; accordingly a detailed description is not provided.

FIG. 9 illustrates one embodiment of the switch circuitry of FIG. 7. Switch circuitry 750 is configured to receive the column logic outputs Z 840 from control logic 710, the segment one enable signals 541, and the segment one data 531 and segment two data 532 of input data 508. The column logic outputs Z 840 are used to selectively enable a bit of the segment two data 532 for multiplexing with a bit of the segment one data 531. The segment one enable signals 541 are used to selectively enable either a segment one data 531 bit or the selected bit of the segment two data 532 for output as a comparand 509 bit.

More particularly, in one embodiment, the switch circuitry 750 includes one or more input multiplexers 950.sub.1 to 950.sub.N and one or more output multiplexers 960.sub.1 to 960.sub.N. Each of the input multiplexers 950.sub.1 to 950.sub.N has M number of data inputs. Each of the input multiplexers 950.sub.1 to 950.sub.N is coupled to receive corresponding segment two data 532 bits at its data inputs. Each of the input multiplexers 950.sub.1 to 950.sub.N is also coupled to receive a corresponding group of column logic outputs 841 as control inputs that selectively outputs one of the segment two data 532 bits.

Each of the output multiplexers 960.sub.1 to 960.sub.N has two data inputs. Each of the output multiplexers 960.sub.1 to 960.sub.N is coupled to receive a corresponding one of the segment one data 532 bits on a first data input and a corresponding one of the outputs of the input multiplexers 950.sub.1 to 950.sub.N on a second data input. Each of the output multiplexers 960.sub.1 to 960.sub.N are also coupled to receive a corresponding one of the segment one enable signals 541 as a control input that selectively outputs either the segment one data 531 bit or the selected segment two data 532 bit for output as a bit C.sub.1 to C.sub.N of comparand 509.

The term "multiplexer" used herein refers to any component or configuration of circuitry that enables the selection of an output from among multiple data inputs based on the application of one or more control signals.

Referring now to both of FIGS. 8 and 9, it should be noted where segment two data 532 contains only a single bit for replacement of one of the segment one data 531 bits, control logic 710 need not be used. Rather, the segment two data 532 bit may be directly coupled to a data input of an output multiplexer 960 of switch circuitry 750 and the segment one enable signal 541 (corresponding to the segment one data 532) may be directly coupled as a control input to an output multiplexer 960 (without the need for control logic 710 or an input multiplexer 950 to select among multiple segment two data 532 bits).

An advantage of the control logic and switching scheme of filter circuit 506 is that it is scaleable such that a larger matrix can be used to handle smaller input data 508 strings (smaller size segment one data and/or segment two data than the number of columns and/or rows, respectively) by applying, for example, "0"s as the A and B operands for the logic cells in unused columns and/or rows of the matrix. Alternatively, the logic cells may be configured such that "1" applied to the A and B operands for logic cells in unused columns and/or rows of the matrix. Moreover, due to the similarity of the cells, the matrix can easily be expanded in a design to readily accommodate large input data strings. Other advantages of the architecture of filter circuit 560 shown in FIGS. 7 and 8, is that it results in a smaller die area and faster timing for large matrixes than with prior filter circuit architectures.

An example of the operation of control logic 710 and switch circuitry 750 is provided below in FIGS. 10A and 10B, respective