Vertical system integration Number:7,402,897 from the United States Patent and Trademark Office (PTO) owispatent The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.<H integration, Vertical, Vertical, system, 7402897.html, Patent, pto, 7402897

Title: Vertical system integration

Abstract: The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

Patent Number: 7,402,897 Issued on 07/22/2008 to Leedy

Inventors: Leedy; Glenn J. (Saline, MI)
Assignee: Elm Technology Corporation (Saline, MI)

Appl. No.: 10/485,046

Filed: August 8, 2003

PCT Filed: August 08, 2003

PCT No.: PCT/US03/25048

371(c)(1),(2),(4) Date: January 22, 2004

PCT Pub. No.: WO2004/015764

PCT Pub. Date: February 19, 2004

Current U.S. Class: 257/678 ; 257/686; 438/106

Current International Class: H01L 21/00 (20060101)

Field of Search: 257/678,686,109 438/106

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Primary Examiner: Schillinger; Laura M.

Claims

What is claimed is:

1. A method of making a stacked integrated circuit comprising: providing a design library comprising a plurality of physical IC designs of fabricated circuit layers, wherein a circuit layer is from the group of an integrated circuit and a stacked integrated circuit; and using at least one circuit layer from the design library to fabricate the stacked integrated circuit, wherein said circuit layer is designed with interconnections that are completed during fabrication of the stacked integrated circuit and said interconnections pass through said circuit layer forming independent signal paths.

2. The method of claim 1, wherein the first and second layers are part of an integrated circuit design library of fabricated circuit layers for use in a stacked IC.

3. The method of claim 2, wherein the integrated circuit design library of fabricated circuit layers for use in a stacked IC includes designs for a plurality of different chip sizes, and the first and second layers are selected to have the same chip size.

4. The method of claim 1, wherein the first and second layers are designed independently of design of the stacked integrated circuit.

5. The method of claim 1, wherein design of the first and second layers and design of the stacked integrated circuit are unrelated.

6. The method of claim 1, comprising: for at least one layer of the stacked integrated circuit, designing a custom design at the time of design of the stacked integrated circuit.

7. The method of claim 1, comprising bonding together the circuit layers such that no integrated circuitry surface of a circuit layer of the stacked integrated circuit is external to the stacked integrated circuit.

8. The method of claim 1, comprising: bonding the circuit layers using an inorganic thermal diffusion bonding process; thinning at least one circuit layer from the backside thereof; and on the backside of the at least one circuit layer, fabricating at least one of active circuit devices, passive circuit devices and horizontal interconnections.

9. The method of claim 1, wherein at least one of the circuit layers comprises electronic circuitry.

10. The method of claim 1, wherein at least one of the circuit layers comprises optical circuitry.

11. The method of claim 1, wherein at least one of the circuit device layers comprises a MEMS device.

12. The method of claim 1, wherein at least one circuit layer is fabricated using a substrate having a plurality of barrier layers formed therein.

13. The method of claim 1, comprising performing IC device fabrication on the backside of one or more circuit layers.

14. The method of claim 13, wherein the IC devices comprise at least one of the following: transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

15. The method of claim 13, wherein the IC devices comprise at least two of the following: transistors, memory cells, resistors, capacitors, indactors, radio frequency antennas and horizontal interconnections.

16. The method of claim 13, wherein the IC devices comprise all of the following: transistors, memory cells, resistors, capacitors, inductors, radio frequency antennas and horizontal interconnections.

17. The method of claim 1, comprising making the stacked integrated circuit without fabrication of a circuit layer specific to the function of the particular stacked integrated circuit.

18. The method of claim 1, wherein fewer than all of the circuit layers are fabricated for the specific function of the particular stacked integrated circuit.

19. The method of claim 1, wherein IC device fabrication is performed on the backside of one or more circuit layers.

20. The method of claim 1, wherein one or more the circuit layers is thinned by removing the substrate to a barrier layer comprising a thin dielectric layer.

21. The method of claim 20, wherein the thin dielectric layer thickness is less than 100 .ANG..

22. The method of claim 20, wherein the thin dielectric layer thickness is less than 200 .ANG..

23. The method of claim 20, wherein the thin dielectric layer thickness is in a range of 50 .ANG. to 500 .ANG..

24. The method of claim 1, wherein a dielectric layer is deposited on the backside of one or more the circuit layers to enhance electrical isolation of an underlying semiconductor device layer.

25. The method of claim 1, wherein IC device fabrication is performed on the backside of one or more circuit layers to complete the fabrication of IC devices partially formed on the front side of the one or more circuit layers.

26. The method of claim 1, wherein IC fabrication is performed on the backside of one or more the circuit layers to fabricate one or more layer memory layers.

27. The method of claim 26, wherein the memory layers consist of at least one of MRAM, PRAM, ferroelectric or dendritic memory.

28. The method of claim 1, wherein the circuit layers are bonded using bonding layers made from two or more metal films one of which has a lower melting temperature and which will diffuse with an immediately adjacent film.

29. The method of claim 28, wherein bonding layers are diffused metal films having a higher melting point than the lower melting point metal film.

30. The method of claim 1, comprising bonding IC substrates using at least two metal films with different melting points on each surface of the substrates to be bonded wherein during or after bonding of the substrates the metal films diffuse to form one metal film with a melting point that is higher than the lower melting point of one of the original two metal films.

31. The method of claim 1, comprising bonding a plurality of circuit layers bonded using one or more bonding layers made from Sn and Al films wherein the Sn film prevents the formation of AI oxide on the Al film and diffuses into the Al film when bonded to another circuit layer.

32. The method of claim 1, comprising: making design changes to a circuit layer; causing the circuit layer to be fabricated; and stacking the circuit layer together with a plurality of other previously-fabricated circuit layers; wherein the design changes to the circuit layer do not require the other circuit layers be fabricated again.

33. The method of claim 1, wherein an application-specific function of the stacked IC is derived from the choice and quantity of circuit layers from previously-fabricated, non-application-specific circuit layers.

34. The method of claim 1, wherein interconnections of circuitry on at least one of the circuit layers are changed by interconnections on the backside of the circuit layer.

35. The method of claim 1, comprising processing both sides of an IC substrate having a frontside and a backside wherein the IC substrate is bonded face down onto a second substrate and the backside of the IC substrate is thinned to a thickness that permits conventional IC fabrication processing, further comprising forming interconnections between circuitry on the frontside of the IC substrate with the circuitry formed on the backside of the IC substrate.

36. The method of claim 1, comprising back biasing one or more transistor gates of at least one circuit layer by forming a contact on the backside of the at least one circuit layer opposite the one or more transistor gates.

37. The method of claim 1, wherein I/O drivers for the stacked IC are physically on a separate circuit layer or on the backside of one of the circuit layers.

38. The method of claim 1, comprising predominately removing dielectric in one of the circuit layers leaving free-standing metal horizontal and vertical interconnections.

39. The method of claim 1, wherein the circuit layers are provided from an inventory of substrates with completed circuitry thereon.

40. The method of claim 1, comprising aligning two substrates or wafers having circuitry thereon for bonding, wherein an opening is made from a backside of one of the substrates or wafers to be bonded to expose an alignment mark, thereby allowing the use of optical alignment methods.

41. The method of claim 1, comprising aligning two substrates or wafers with circuitry thereon for bonding, wherein an opening is made from a backside forming an opening on the front side of one of the substrates or wafers to be bonded exposing an alignment mark, and using an atomic force microscope to access alignment marks on both substrates or wafers at the same time.

42. The method of claim 1, wherein the stacked IC comprises a stacked programmable logic device having at least one of a programmable gate circuit layer and a memory circuit layer, comprising adding to the stacked programmable logic device one or more programmable gate circuit layers or memory circuit layers.

43. The method of claim 1, whererin the library is composed of a plurality of fabricated IC, stacked integrated circuit and MEMS designs designed to be used in a stacked integrated circuit.

44. The method of claim 1, whererin at least one of the circuit layers has a principle surface with active circuitry formed thereon and contacts formed on the surface opposite the principle surface.

45. The method of claim 1, wherein at least one of the following is performed: deposition of a dielectric layer on the backside of one or more of the circuit layers to enhance electrical isolation of an underlying semiconductor device layer; fabrication of one or more IC devices on the backside of one or more circuit layers to complete the fabrication of IC devices partially formed on the front side of the one or more circuit layers; fabrication of IC devices on the backside of one or more circuit layers to fabricate one or more memory layers consisting of at least one or MRAM, PRAM, ferroelectric and dendritic memory.

Description

The diversity of circuit function and operational requirements that underlay the implementation of a broad range of integrated circuit applications including what is commonly referred to as a SoC [System on a Chip] demand widely varying semiconductor fabrication processes and/or technologies without further consideration being given to the integration of optical and MEMS technologies with those semiconductor technologies. Limitations on the electronic industry's capability to meet these ever greater demands has made the implementation of numerous integrated circuit and SoC products impossible or beyond acceptable manufacturing costs.

The Vertical System Integration (VSI) invention herein is a method for integration of disparate electronic, optical and MEMS technologies into a single integrated circuit die or component and wherein the individual device layers used in the VSI fabrication processes are preferably previously fabricated components intended for generic multiple application use and not necessarily limited in its use to a specific application. The VSI method of integration lowers the cost difference between lower volume custom electronic products and high volume generic use electronic products by eliminating or reducing circuit design, layout, tooling and fabrication costs.

The VSI invention achieves its novel methods of integration through high precision alignment and stacking of component layers, fine grain vertical interconnections, thin flexible circuit substrates fabricated using stress-controlled dielectrics and low temperature compo