Vertical transistors Number:7,521,322 from the United States Patent and Trademark Office (PTO) owispatent Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.<H transistors, Vertical, Vertical, transi, 7521322.html, Patent, pto, 7521322

Title: Vertical transistors

Abstract: Vertical transistors for memory cells, such as 4F2 memory cells, are disclosed. The memory cells use digit line connections formed within the isolation trench to connect the digit line with the lower active area. Vertical transistor pillars can be formed from epitaxial silicon or etched from bulk silicon. Memory cells can be formed by creating a cell capacitor electrically connected to each transistor pillar.

Patent Number: 7,521,322 Issued on 04/21/2009 to Tang, et al.

Inventors: Tang; Sanh Dang (Boise, ID), Haller; Gordon A. (Boise, ID)
Assignee: Micron Technology, Inc. (Boise, ID)

Appl. No.: 11/491,066

Filed: July 21, 2006

Related U.S. Patent Documents


Application Number	Filing Date	Patent Number	Issue Date
10934621	Sep., 2004	7285812

Current U.S. Class: 438/270 ; 438/137; 438/212; 438/259; 438/696

Current International Class: H01L 29/72 (20060101)

Field of Search: 438/137,212,259,270,696

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Primary Examiner: Wojciechowicz; Edward
Attorney, Agent or Firm: Wells St. Johnn P.S.

Parent Case Text

This application is a divisional of U.S. application Ser. No. 10/934,621, titled "Vertical Transistors", filed on Sep. 2, 2004 now U.S. Pat. No. 7,285,812, the entirety of which is hereby incorporated herein by reference.

Claims

We claim:

1. A method of forming an integrated circuit including a vertical transistor comprising: defining a ridge in a ridge region and a trench adjacent to the ridge in a substrate; forming a bit line within the trench; depositing an insulating material in the trench to isolate the bit line; forming a transistor pillar over the ridge region after depositing the insulating material in the trench, wherein the ridge is adjacent to the trench and extends from a bottom level of the trench to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, wherein the transistor pillar extends upwardly from the shoulder of the ridge, wherein the trench extends from the bottom level to the shoulder, and wherein the bit line is below the shoulder within the trench; exposing a portion of the bit line adjacent to the ridge region after forming the transistor pillar; creating a bit line stitch within the trench connecting the bit line to a lower active area within the ridge region after exposing the portion of the bit line, providing the lower active area to comprise one source/drain region of the vertical transistor; forming a gate surrounding the transistor pillar after creating the bit line stitch; and providing a lower portion of the pillar to comprise a channel region of the vertical transistor and providing an upper region of the pillar to comprise another source/drain region of the vertical transistor.

2. The method of claim 1, further comprising forming a gate dielectric surrounding the transistor pillar.

3. The method of claim 1, wherein creating the bit line stitch comprises depositing polysilicon.

4. The method of claim 3, wherein depositing polysilicon comprises depositing polysilicon with dopants.

5. The method of claim 4, wherein creating the bit line stitch comprises outdiffusing the dopants to form the lower active area.

6. The method of claim 1, wherein forming the transistor pillar comprises forming an epitaxial silicon pillar.

7. A method of forming an integrated circuit comprising a plurality of field effect transistors, individual of the field effect transistors comprising a pair of source/drain regions, a gate comprised by a word line, and a channel region, the method comprising: forming a bit line within each of a plurality of trenches in a substrate; forming a plurality of transistor pillars on each of a plurality of ridges in the substrate after forming the bit lines, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, each transistor pillar extending upwardly from the shoulder of the ridge, the bit line being buried below the shoulder in each trench, wherein forming the transistor pillars comprises defining a column of transistor pillars on each ridge and rows of transistor pillars across different ridges, wherein the plurality of ridges alternate with and separate the plurality of trenches; forming a word line to connect each row of transistor pillars; creating a plurality of exposed bit line windows in the trenches after forming the word lines; forming a bit line stitch in each exposed bit line window to connect the bit lines to individual lower active areas received beneath individual of the transistor pillars;and providing individual of the lower active areas to comprise one of the pair of source/drain regions of one of the field effect transistors and providing the individual transistor pillars received over the respective lower active areas to comprise the channel region and the other of the pair of source/drain regions of the same one of the field effect transistors.

8. The method of claim 7, further comprising forming a capacitor electrically connected to the other of the pair of source/drain regions over each of the transistor pillars.

9. The method of claim 8, wherein forming the capacitor comprises forming a container capacitor.

10. The method of claim 7, wherein forming the bit line stitch comprises depositing polysilicon.

11. The method of claim 10, wherein forming the bit line stitch comprises depositing polysilicon with n-dopants.

12. The method of claim 11, further comprising outdiffusing the n-dopants in the bit line stitch into the substrate to form the lower active area of each transistor.

13. The method of claim 7, wherein forming the transistor pillars comprises: forming a first mask having a plurality of lines over the substrate; forming a second mask between the lines of the first mask wherein the first mask and the second mask form a plurality of exposed substrate islands; providing a spacer layer over the first mask and lining the second mask and the exposed substrate islands; punching a contact through the spacer layer to the exposed substrate islands; and growing epitaxial silicon within the exposed substrate island after punching the contact.

14. A method of forming an integrated circuit comprising a plurality of field effect transistors, individual of the field effect transistors comprising a pair of source/drain regions, a gate comprised by a word line, and a channel region, the method comprising: forming a plurality of trenches separating a plurality of plateaus within a substrate; depositing a bit line in each trench; isolating the bit line within each trench; forming an exposed side portion of the bit line; depositing a bit line strap connecting the exposed side portion of the bit line to a plurality of lower active areas in the plateaus; etching the plateaus to form transistor pillars and ridges in the substrate, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, each transistor pillar extending upwardly from the shoulder of the ridge, the bit line being buried below the shoulder in each trench; depositing a word line material surrounding the transistor pillars; forming vertical self-alignment spacers surrounding an upper portion of the transistor pillars and over the word line material; etching the word line material to form a plurality of word lines connecting a row of transistor pillars; and providing individual of the lower active areas to comprise one of the pair of source/drain regions of one of the field effect transistors and providing the individual transistor pillars received over the respective lower active areas to comprise the channel region and the other of the pair of source/drain regions of the same one of the field effect transistors.

15. The method of claim 14, wherein the substrate comprises bulk silicon.

16. The method of claim 14, wherein depositing the bit line strap comprises depositing polysilicon.

17. The method of claim 16, wherein depositing the bit line strap comprises depositing polysilicon with n-dopants.

18. The method of claim 17, further comprising outdiffusing the n-dopants in the bit line strap into the substrate to form the lower active areas.

19. The method of claim 14, wherein etching the plateaus to form transistor pillars comprises: forming a first mask over the substrate, wherein the first mask has a plurality of holes depositing a second mask within the holes of the first mask; removing the first mask after depositing the second mask; and etching the substrate selectively to the second mask to form transistor pillars.

20. The method of claim 14, further comprising forming a capacitor over and electrically connected to each transistor pillar.

21. The method of claim 20, wherein forming the capacitor comprises forming a container capacitor.

22. A method of forming vertical transistors for a memory array comprising: forming a plurality of buried bit lines within a plurality of trenches in a substrate, the plurality of trenches being separated by a plurality of ridges, each ridge extending from a bottom level of the trenches to a shoulder of the ridge, wherein the shoulder of the ridge defines an upper surface of the ridge, each trench extending from the bottom level to the shoulder, the bit line being buried below the shoulder in each trench,; depositing a first mask on the substrate over the trenches and the ridges; forming a plurality of holes in the first mask; depositing a second mask in the holes of the first mask removing the first mask after depositing the second mask; etching the substrate selectively to the second mask to form a plurality of transistor pillars extending above and adjacent to the buried bit lines, each transistor pillar extending upwardly from the shoulder of the ridge; and providing individual of the transistor pillars to comprise a channel region and one source/drain region of an individual of the vertical transistors, another source/drain region of said individual of the vertical transistors being provided to be received within the ridge beneath said individual of the transistor pillars.

23. The method of claim 22, wherein forming the plurality of holes in the first mask comprises forming holes in the first mask over the ridges.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to the field of integrated circuit fabrication, specifically to the formation of transistors.

2. Description of the Related Art

Since the introduction of the digital computer, electronic storage devices have been a vital resource for the retention of data. Conventional semiconductor electronic storage devices, such as Dynamic Random Access Memory (DRAM), typically incorporate capacitor and transistor structures in which the capacitors temporarily store data based on the charged state of the capacitor structure. In general, this type of semiconductor Random Access Memory (RAM) often requires densely packed capacitor structures that are easily accessible for electrical interconnection.

In order to increase efficiency of memory devices, there is an effort to create smaller memory cells. DRAM memory cells can shrink in several ways. One way to decrease the size of a memory cell is to reduce the minimum feature size (F). This generally occurs through new and advanced lithography and etching techniques. Memory cells can also be decreased by designing a smaller memory cell. For example, many of the DRAM chips on the market today have a memory cell size of 8F.sup.2 or greater, where F is the dimension of the minimum feature for a given manufacturing process.

U.S. Pat. No. 6,734,482 issued to Tran, et al., describes the use of a bit line buried within an isolation trench. The memory cell described in that patent is a 6F.sup.2 memory cell. A conductive strap connects the bit line to the active area (source) of a planar transistor which does not use a vertical pillar. However, these designs can take up more chip real estate.

Vertical transistor designs can be used to decrease chip real estate occupied by a memory cell transistor. An example of a memory cell with a vertical transistor is disclosed in U.S. Pat. No. 6,756,625, issued to Brown, the disclosure of which is incorporate by reference herein. In that patent, the digit line is directly connected to a pillar used in the vertical transistor. However, this can be difficult to integrate into the process flow of a DRAM memory cell. Therefore, additional methods of forming vertical transistors are desirable.

SUMMARY OF THE INVENTION

In an aspect of the invention, a memory array is disclosed. The array comprises a substrate having a plurality of ridges and trenches. A digit line is within each of the plurality of trenches. A plurality of transistor pillars overlies each of the plurality of ridges. The transistor pillars include an upper active area. A plurality of lower active areas is in an upper surface of each of the plurality of ridges. One of the lower active areas neighbors each transistor pillar. A digit line link is within each trench connecting each lower active area to one digit line. The array also includes a plurality of word lines, wherein each word line surrounds a row of transistor pillars over at least two of the plurality of ridges.

In another aspect of the invention, a method of forming an integrated circuit including a vertical transistor is disclosed. The method comprises defining a ridge region and a trench in a substrate. A digit line is formed within the trench. An insulating material is deposited in the trench to isolate the digit line. A transistor pillar is formed in the ridge region after depositing the insulating material in the trench. A portion of the digit line adjacent to the ridge region is exposed after forming the transistor pillar. A digit line stitch is created within the trench connecting the digit line to a lower active area within the ridge region after exposing the portion of the digit line. A gate surrounding the transistor pillar is formed after depositing the digit line stitch.

A method of forming a memory array is disclosed in another aspect of the invention. The method comprises forming a digit line within each of a plurality of trenches in a substrate. A plurality of transistor pillars is produced on each of a plurality of ridges in the substrate after forming the digit lines. Forming the pillars comprises forming a column of transistor pillars on each ridge and rows of transistor pillars across different ridges. A word line is formed to connect each row of transistor pillars. A plurality of exposed digit line windows is created in the trench after forming the word lines. The method further comprises forming a digit line stitch in each exposed digit line window to connect the digit lines to a lower active area of one neighboring transistor.

In another aspect of the invention, a method of forming a memory array is disclosed. The method comprises forming a plurality of trenches and a plurality of plateaus within a substrate. A digit line is deposited in each trench and the digit line is isolated within each trench. An exposed side portion of the digit line is formed and a digit line strap is deposited to connect the exposed side portion of the digit line to a plurality of lower active areas in the plateaus. The plateaus are etched to form transistor pillars and ridges in the substrate. A word line material surrounding the transistor pillars is deposited. Vertical self-alignment spacers are formed surrounding an upper portion of the transistor pillars and over the word line material. The method further comprises etching the word line material to form a plurality of word lines connecting a row of transistor pillars.

A method of forming vertical transistor pillars in a substrate is disclosed in another, aspect of the invention. The method comprises forming a plurality of buried digit lines within a plurality of trenches in a substrate. A first mask is deposited on the substrate. A plurality of holes is formed in the first mask. A second mask is deposited in the holes of the first mask. The first mask is removed after depositing the second mask. The method further comprises etching the substrate selectively to the second mask to form a plurality of pillars in the substrate above and adjacent to the buried digit lines.

In another aspect of the invention, a vertical transistor for an integrated circuit is disclosed. The transistor comprises a buried digit line within a trench in a bulk semiconductor substrate. A bulk semiconductor transistor pillar is on a ridge in the semiconductor substrate. A digit line link is in the trench connecting the buried digit line to a lower active area in the ridge. The transistor further comprises a conductive gate surrounding the transistor pillar.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic plan view of a memory array at a first stage of processing.

FIG. 1B is a schematic cross-section of the array of FIG. 1A along line 1B-1B of FIG. 1A.

FIG. 2A is a schematic plan view of the memory array of FIG. 1A after removing part of the trench oxide and depositing a space holder.

FIG. 2B is a schematic cross-section of the array of FIG. 2A along line 2B-2B of FIG. 2A.

FIG. 3A is a schematic plan view of the memory array of FIG. 2A after recessing the space holder.

FIG. 3B is a schematic cross-section of the array of FIG. 3A along line 3B-3B of FIG. 3A.

FIG. 4A is a schematic plan view of the memory array of FIG. 3A after deposition of a strap material.

FIG. 4B is a schematic cross-section of the array of FIG. 4A along line 4B-4B of FIG. 4A.

FIG. 5A is a schematic plan view of the memory array of FIG. 4A after removing a cap over substrate ridges and patterning a masking layer.

FIG. 5B is a schematic cross-section of the array of FIG. 5A along line 5B-5B of FIG. 5A.

FIG. 6A is a schematic plan view of the memory array of FIG. 5A after an etch step.

FIG. 6B is a schematic cross-section of the array of FIG. 6A along line 6B-6B of FIG. 6A.

FIG. 7A is a schematic plan view of the memory array of FIG. 6A after a spacer formation and an oxidation process.

FIG. 7B is a schematic cross-section of the array of FIG. 7A along line 7B-7B of FIG. 7A.

FIG. 8A is a schematic plan view of the memory array of FIG. 7A after stripping spacers, forming a gate dielectric, and depositing a word line material.

FIG. 8B is a schematic cross-section of the array of FIG. 8A along line 8B-8B of FIG. 8A.

FIG. 9A is a schematic plan view of the memory array of FIG. 8A after forming self-alignment spacers and patterning word lines.

FIG. 9B is a schematic cross-section of the array of FIG. 9A along line 9B-9B of FIG. 9A.

FIG. 9C is a schematic cross-section of the array of FIG. 9A along line 9C-9C of FIG. 9A

FIG. 10A is a schematic plan view of the memory array of FIG. 9A after depositing and planarizing an insulation layer.

FIG. 10B is a schematic cross-section of the array of FIG. 10A along line 10B-10B of FIG. 10A.

FIG. 10C is a schematic cross-section of the array of FIG. 10A along line 10C-10C of FIG. 10A

FIG. 11 is a schematic cross-section of the array of FIG. 10A after forming a lower capacitor electrode over each transistor.

FIG. 12A is a schematic plan view of a partially fabricated memory array in another preferred embodiment, showing a pattern of buried digit lines in parallel trenches.

FIG. 12B is a schematic cross-section of the array of FIG. 12A along line 12B-12B of FIG. 12A.

FIGS. 13A-13C schematically illustrate the memory array of FIG. 12A after depositing and patterning a first mask of lines crossing the digit line trenches.

FIGS. 14A-14C schematically illustrate the memory array of FIG. 13A rotated 90 degrees after forming a second mask to form exposed substrate windows, depositing a spacer in the exposed substrate windows and forming pillars epitaxially.

FIGS. 15A-15C schematically illustrate the memory array of FIG. 14A after forming word lines, an insulating layer, and a sacrificial mask.

FIGS. 16A-16C schematically illustrate the memory array of FIG. 15A after re-patterning the first mask and etching to expose lower active areas.

FIGS. 17A-17E schematically illustrate the memory array of FIG. 16A after exposing the digit line and depositing a spacer mask around the word lines.

FIGS. 18A-18E schematically illustrate the memory array of FIG. 17A -17E after forming stitches connecting the digit line with a lower active area.

FIGS. 19A-19C schematically illustrate the memory array of FIG. 18A after the removal of insulating materials over the pillars.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductor materials, including, but not limited to, bulk semiconductor materials such as a semiconductor wafers, and semiconductor material layers. The term "substrate" refers to any supporting substrate, including, but not limited to, the semiconductor substrates (either alone or in assemblies comprising other materials thereon) described above. Also in the context of this document, the term "layer" encompasses both the singular and the plural unless otherwise indicated.

Processes for forming vertical surround gate transistors (VSGTs), memory cells comprising VSGTs and arrays of same are disclosed. Preferably, the memory cells have a cell size of 4F.sup.2. In preferred embodiments, transistors are formed without using a separate interconnect outside of the isolation trench to connect a buried digit line and a lower active area. A digit line link within the isolation trench is used to connect the digit line to the lower active area. In one embodiment, a strap running the length of the array connects the digit line to the lower active area of several transistors in a row. In another embodiment, a conductive stitch is used to separately connect the digit line to the lower active area of one transistor. Additionally by using a buried digit line in the STI trench and strapping the buried digit line to the active area, less chip real estate is used than using other digit line placements.

Strapping the Digit Line to the Lower Active Area of Several Transistors

VSGTs can be formed using epitaxially grown silicon to form the pillar surrounded by the vertical surround gate (VSG). However, epitaxially grown silicon often has high defect rates. It is challenging to overcome these defects or to form a defect free epitaxially grown silicon pillar, and also to integrate the process flow with digit line formation and contact. In one preferred embodiment, epitaxially grown silicon is not used, rather etch steps are used to define the transistor pillar. This eliminates the challenges of dealing with epitaxially-grown silicon.

In a preferred embodiment illustrated in FIG. 11, buried digit lines (BDL) 40 are placed in shallow trench isolation (STI) trenches 12 within an array 2. The buried digit lines 40 are preferably connected to a lower active area 65, which is formed in an upper surface of the substrate 10, by a strap 60 within the trench 12. By strapping the buried digit line 40 to the lower active area 65, a separate interconnect becomes unnecessary. The word line 95 is preferably positioned above the buried digit line 40.

Referring now to FIG. 1A, a schematic planar view of a portion of an array 2 can be seen. Trenches 12 are seen lined with an insulation material 30, between a pair of cap lines 25 over the substrate 10. The trenches are filled with an insulation material 45 (FIG. 1B) after depositing a digit line 40 (FIG. 1B) in each trench 12. For simplicity, FIG. 1A shows only the lining insulation material 30 within the trenches 12. Preferably the trench liner 30 and the trench filler 45 are similar mat