Visible/near infrared image sensor array Number:7,436,038 from the United States Patent and Trademark Office (PTO) owispatent

Title: Visible/near infrared image sensor array

Abstract: A MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count. Further advantages of the invention include low electrical bias voltages, low power consumption, compact packaging, and radiation hardness. In special preferred embodiments CMOS stitching technology is used to provide multi-million pixel focal plane array sensors. One embodiments of the invention made without stitching is a two-million pixel sensor. Other preferred embodiments available using stitching techniques include sensors with 250 million (or more) pixels fabricated on a single wafer. A particular application of these very high pixel count sensors is as a focal plane array for a rapid beam steering telescope in a low earth orbit satellite useful for tracking over a 1500-meter wide track with a resolution of 0.3 meter.

Patent Number: 7,436,038 Issued on 10/14/2008 to Engelmann,   et al.

---

Inventors:	Engelmann; Michael G. (Pukalani, HI), Chao; Calvin (Cupertino, CA), Hsieh; Tzu-Chiang (Fremont, CA), Martin; Peter (Kahului, HI), Pender; Milam (Kihei, HI)
Assignee:	e-Phocus, Inc (San Jose, CA)
Appl. No.:	10/785,833
Filed:	February 23, 2004

---

Related U.S. Patent Documents

---

	Application Number	Filing Date	Patent Number	Issue Date
	10746529	Dec., 2003
	10648129	Aug., 2003	6809358
	10371618	Feb., 2003	6730900
	10229953	Aug., 2002
	10229954	Aug., 2002	6791130
	10229955	Aug., 2002	7411233
	10229956	Aug., 2002	6798033
	10072637	Feb., 2002	6730914

---

Current U.S. Class:	257/444 ; 257/233; 257/258; 257/291; 257/292; 257/461; 257/462; 257/E27.133
Current International Class:	H01L 31/00 (20060101)
Field of Search:	257/118,222,229,233,234,257,258,290,291,292,461,462,444,E27.133

---

References Cited [Referenced By]

---

U.S. Patent Documents

4759947	July 1988	Ishihara et al.
5599403	February 1997	Kariya et al.
5665959	September 1997	Fossum et al.
6252218	June 2001	Chou
6399873	June 2002	Sano et al.
6759262	July 2004	Theil et al.

Primary Examiner: Pert; Evan
Assistant Examiner: Tran; Tan N
Attorney, Agent or Firm: Ross; John R.

---

Parent Case Text

---

This application is a continuation in part of U.S. patent application Ser. No. 10/746,529, filed Dec. 23, 2003; Ser. No. 10/648,129 filed Aug. 26, 2003 now U.S. Pat. No. 6,809,358; Ser. No. 10/371,618, filed Feb. 22, 2003 now U.S. Pat. No. 6,730,900; Ser. No. 10/229,953 filed Aug. 27, 2002; Ser. No. 10/229,954 filed Aug. 27, 2002 now U.S. Pat. No. 6,791,130; Ser. No. 10/229,955 filed Aug. 27, 2002 now U.S. Pat. No. 7,411,233; Ser. No. 10/229,956 filed Aug. 27, 2002 now U.S. Pat. No. 6,798,033 and Ser. No. 10/072,637 filed Feb. 5, 2002 now U.S. Pat. No. 6,730,914. This patent application relates to image sensors and in particular to broad spectrum image sensors covering spectral ranges within the visible and near infrared spectral ranges.

---

Claims

---

We claim:

1. A MOS or CMOS based visible/near infrared sensor array comprising: A) a substrate, B) a plurality of MOS or CMOS pixel circuits fabricated in or on said substrate, each pixel circuit comprising: 1) a charge collecting electrode for collecting electrical charges and 2) a plurality of transistors for monitoring periodically charges collected by said charge collecting electrode, C) a continuous un-pixelated photodiode layer of charge generating material located above said pixel circuits for converting into electrical charges electromagnetic radiation in the visible and near infrared spectral ranges, said photodiode layer comprising at least an n-layer, an intrinsic layer and a p-layer, wherein each of the n-layer, the intrinsic layer and the p-layer of the continuous un-pixelated photodiode layer are continuous with no gaps between pixels, and wherein one of said n-layer or said p-layer is adjacent to the charge collecting electrodes in each of the pixel circuits to define a bottom layer; and wherein the bottom layer comprises sufficient carbon to increase its electrical resistance to more than 2.times.10.sup.7 ohm-cm to minimize pixel-to-pixel crosstalk; and D) a surface electrode in the form of a grid or thin transparent layer located above said layer of charge generating material.

2. The sensor as in claim 1 wherein said charge generating material also converts electromagnetic radiation in ultraviolet spectral ranges into electrical charges.

3. The sensor as in claim 2 wherein said surface electrode is comprised of indium tin and oxygen.

4. The sensor as in claim 2 wherein said plurality of pixel circuits in at least 2 million CMOS pixel circuits.

5. The sensor as in claim 1 wherein one of the said intrinsic layer comprises microcrystalline silicon.

6. The sensor as in claim 5 wherein said microcrystalline layer is grown using a radio frequency plasma enhanced chemical vapor deposition process.

7. The sensor as in claim 1 wherein the said intrinsic layer is comprised entirely of microcrystalline silicon.

8. The sensor as in claim 1 wherein said p-layer is comprised of copper selenium and indium and said n-layer is comprised of cadmium and sulfur.

9. The sensor as in claim 8 wherein said p-layer also comprises gadolinium.

10. The sensor as in claim 9 wherein said n-layer is on top of said p-layer.

11. The sensor as in claim 10 wherein said p-layer is deposited from a four crucible vapor.

12. The sensor as in claim 1 wherein said photodiode layer comprises geranium.

13. The sensor as in claim 1 wherein said photodiode layer comprises microcrystalline germanium.

14. The sensor as in claim 1 wherein said surface electrode is comprised of indium tin and oxygen.

15. The sensor as in claim 1 wherein said p-layer is located adjacent to said surface electrode.

16. The sensor as in claim 1 wherein said plurality of pixel circuits in at least 2 million CMOS pixel circuits.

17. The sensor as in claim 1 wherein said plurality of pixel circuits in at least 100 million CMOS pixel circuits.

18. The sensor as in claim 1 wherein said pixel circuits are located on a single wafer and are comprised of pixels produced in die spots that are lithographically stitched together to form a unitary pixel array of more than 50 million pixels.

19. The sensor as in claim 18 wherein said array of more than 50 million pixels is an array of more than 100 million pixels.

20. An array as in claim 1 and also comprising data analyzing circuits fabricated on said substrate.

21. An array as in claim 1 wherein said sensor is configured with a Column-Parallel Analog-to Digital architecture.

22. An array as in claim 1 where said array is a component of a video camera and said array further comprises two 10-bit output ports representing video output from columns and odd columns respectively.

23. An array as in claim 1 wherein said surface electrode is comprised of a layer of indium tin oxide.

24. An array as in claim 1 and further comprising an array of color filters located on top of said surface electrode.

25. An array as in claim 24 wherein said color filters are comprised of red, green and blue filters arranged in four color quadrants of two green, one red and one blue.

26. An array as in claim 1 wherein said array is a part of a camera incorporated into a device chosen from the following group: Analog camcorder Digital camcorder Security camera Digital still camera Personal computer camera Toy Military unmanned aircraft, bomb and missile Sports equipment High definition television camera Telescope ROBS Telescope.

---

Description

---

BACKGROUND OF THE INVENTION

The prior art includes a variety of image sensors. Image sensors operating in the visible and near infrared spectrums have widespread utility for military and commercial applications.

Charge Coupled Devices

Charge coupled device (CCD) image sensors are pixelated readout arrays fabricated on and in a crystalline silicon substrate. These sensors convert incident light to electric charges that are collected in pixels formed in the substrate. Pixelated charge packets are typically transferred to the periphery of the array by a "bucket brigade" technique and are converted to voltage signals by charge sensitive amplifiers located at the periphery of the array. These voltage signals are digitized by an off-chip analog-to-digital converter. The photoresponse of these sensors is typically limited to the 400 nm-900 nm spectral range by the semiconductor bandgap properties of crystalline silicon.

CMOS Image Sensors

Complementary metal-oxide semiconductor (CMOS) sensors are produced using standard CMOS fabrication processes typically utilized for the fabrication of integrated circuits. CMOS sensors, like CCD's convert incident light to electric charge in electronic circuitry fabricated in or on the silicon substrate. The electric charge is electrically measured using multiple-transistors pixel circuitry and readout electronics also fabricated on the silicon die. The CMOS sensor photoresponse typically is also limited to the 400 nm-900 nm spectral range by the semiconductor bandgap properties of crystalline silicon. Also, in prior art CMOS sensors, the CMOS pixel circuitry obscures a major portion of each pixel's photosensitive area, resulting in low collection efficiency.

U.S. Pat. Nos. 5,528,043; 5,886,353; 5,998,794 and 6,163,030 are special examples of prior art patents utilizing CMOS circuits for imaging. These patents describe CMOS sensor technology developed by Applicants and their fellow workers in which a photodiode layer structure is produced in continuous layers on top of active CMOS pixels. U.S. Pat. No. 5,528,043 describes an X-ray detector utilizing a CMOS sensor array with readout circuits on a single chip. In that example image processing is handled by a separate processor. U.S. Pat. No. 5,886,353 describes a generic pixel architecture using a hydrogenated amorphous silicon layer structure in conjunction with CMOS circuits to form the pixel arrays. U.S. Pat. Nos. 5,998,794 and 6,163,030 describe various ways of making electrical contact to the underlying CMOS circuits in a pixel. All of the above U.S. patents are incorporated herein by reference.

Bump-Bonded Sensors

Hybridized bump-bonded sensors are fabricated by mechanically compressing a pixelated crystalline detector to a CMOS readout array. An electrically conductive indium ball located at each pixel provides the pixelated electrical connections. Typical bump-bonded sensors include crystalline silicon (400 nm-900 nm), indium gallium arsenide (900 nm-1600 nm), indium antinomide (3 microns-5 microns), and mercury cadmium telluride (12 microns-14 microns). The bump-bonding process using gallium arsenide or mercury cadmium telluride enables the sensors photoresponse to be extended to spectral regions outside of the crystalline silicon photoresponse. Bump bonding requires fairly large pixel sizes (typically 25-50 microns); this limits the achievable pixel count. To the best of Applicant's knowledge, bump-bonded detectors that span the visible and near infrared spectrum (400 nm-1500 nm) do not presently exist in the prior art.

Image Intensifier Sensors

State-of-the-art third generation (GEN III) night vision image intensifier sensors combine a crystalline gallium arsenide (GaAs) detector with an electrically biased micro-channel plate and a phosphor plate. The micro-channel plate consists of a regular array of open channels (such as an array with 15 micron minimum channel spacing) in a lead oxide glass material. The GaAs detector functions as a photocathode that ejects electrons in response to incident absorbed photons (that could be visible light or near infrared photons) with an efficiency of about 10 to 16 percent. The electrons are accelerated towards the micro-channel plate to produce a very large number of electrons (typically 10.sup.4-10.sup.6) for each incident electron. The electrons from the micro-channel plate are then accelerated to the phosphor plate to produce a visible image on the phosphor plate representing the image of a field of view produced by the incident absorbed photons. The visible image may be viewed with the eye or a visible light image sensor such as a digital camera. Image intensifiers of this type detect photons over a limited spectral bandwidth (400 nm-900 nm). Also as stated above effective quantum efficiencies for these devices, which include noise contributions from the micro-channel plate amplification process, are quite low (10-16%). These devices require a vacuum and a high applied voltage (200 V-800 V) which results in bulky packaging and increased risk of damage. The 15 micron micro-channel spacing results in relatively large effective pixel sizes, which limits the pixel count.

There is a need for an image sensor with enhanced sensitivity, small pixel size and large pixel count that can provide high image performance in spectral ranges that extend beyond the spectral photosensitivity range of crystalline silicon.

SUMMARY OF THE INVENTION

The present invention provides a MOS or CMOS sensor for high performance imaging in broad spectral ranges including portions of the infrared spectral band. These broad spectral ranges may also include portions or all of the visible spectrum, therefore the sensor has both daylight and night vision capabilities. The sensor includes a continuous multi-layer photodiode structure on a many pixel MOS or CMOS readout array where the photodiode structure is chosen to include responses in the near infrared spectral ranges. A preferred embodiment incorporates a microcrystalline copper indium diselenide/cadmium sulfide photodiode structure on a CMOS readout array. An alternate preferred embodiment incorporates a microcrystalline silicon germanium photodiode structure on a CMOS readout array. Each of these embodiments provides night vision with image performance that greatly surpasses the GEN III night vision technology in terms of enhanced sensitivity, pixel size and pixel count. Further advantages of the invention include low electrical bias voltages, low power consumption, compact packaging, and radiation hardness. In special preferred embodiments CMOS stitching technology is used to provide multi-million pixel focal plane array sensors. One embodiment of the invention made without stitching is a two-million pixel sensor. Other preferred embodiments available using stitching techniques include sensors with 250 million (or more) pixels fabricated on a single wafer. A particular application of these very high pixel count sensors is as a focal plane array for a rapid beam steering telescope in a low earth orbit satellite useful for tracking over a 1500-meter wide track with a resolution of 0.3 meter.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A through 1H show features of a 2-million pixel CMOS sensor.

FIG. 2 shows the quantum efficiency versus wavelength of amorphous silicon (a-Si:H) and copper indium diselenide (CIS).

FIG. 3 shows the absorption coefficient and absorption depth for amorphous silicon (a-Si:H), crystalline silicon (c-Si), copper indium diselenide (CIS), and cadmium sulfide (CdS).

FIG. 4 shows the absorption coefficients versus wavelength for amorphous silicon, crystalline silicon, and microcrystalline silicon.

FIG. 5 shows the Raman growth demonstrating microcrystalline growth by PECVD.

FIG. 6 shows the measured QE versus wavelength data for a microcrystalline silicon photodiode structure.

FIG. 7 shows the quantum efficiency versus wavelength of CIS and a GEN III image intensifier, in comparison to the night sky irradiance.

FIG. 8 shows a table of the CIS quantum efficiency and the night sky irradiance versus wavelength.

FIG. 9 shows the signal-to-noise calculations for a CIS POAP image sensor and a GEN III image sensor.

FIG. 10 shows the calculated quantum efficiency versus wavelength of microcrystalline germanium (.mu.c-Ge) for three different i-layer thicknesses.

FIG. 10A shows the predicted QE curves for photodiodes based on .mu.c-Si, .mu.c-Si.sub.0.5Ge.sub.0.5, and .mu.c-Si.sub.0.23Ge.sub.0.77 i-layers.

FIG. 10B shows the predicted performance for a .mu.c-Ge photodiode using c-Ge optical properties as discussed above.

FIG. 11 shows front surface reflection and transmission of light into the i-layer in a .mu.c-Si device with an optimized SiO.sub.2+Ta.sub.2O.sub.5 anti-reflection coating.

FIG. 12A-12E show equipotential plots for continuous (12A) top and bottom electrodes, as well as strip (12B-12E) electrodes with aspect ratios ranging from t=0.1 to 0.6.

FIG. 13A-13F show measured quantum efficiency versus wavelength curves for various devices.

FIG. 14A shows the reticle mask for the specialized CMOS stitching fabrication technique.

FIG. 14B shows the CMOS stitching technique.

FIG. 14C shows a preferred wafer layout for fabricating different sized very large arrays using the CMOS stitching technique.

FIG. 14D shows the overall electronic architecture of each focal plane array.

FIG. 15A-15B shows a low earth orbit (LEO) reconnaissance satellite that utilize the very large FPA and the ROBS optical tracking concept.

FIG. 15C shows the spatial resolution of digital sensors has decreased to mathc the spatial sampling capability of film over the last three decades.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS

Two Million Pixel CMOS Sensor

General Description

Some features of a two-million pixel CMOS sensor are shown in FIGS. 1A through 1H. This sensor is fabricated by depositing a multi-layer photodiode structure on top of an electronic readout array that is fabricated using complimentary metal-oxide semiconductor (CMOS) methods commonly utilized in integrated circuit manufacturing. Absorbed photons create charge pairs in the photodiode structure and the liberated electric charge migrates under the influence of an applied electric field to pixel pads in the CMOS readout array where the charges are stored on capacitors, each capacitor representing a pixel. Active pixel circuitry at each pixel produces an amplified voltage proportional to the stored electric charge. CMOS readout circuitry, that may be located at the periphery of each array column, further amplifies and digitizes the pixel signal. Additional pixel circuitry provides digital multiplexing of the digitized pixel signals, pixel selection during the readout process, and a reset function that discharges the pixel capacitor. The patents listed in the Background Section as well as the parent patent applications listed in the first sentence of this application (all of which patents and patent applications are incorporated herein by reference) provide details of the fabrication and operation of these CMOS sensor arrays in addition to the specific details provided below.

Transistor Portion

Two pixels of the two-million pixels cell array and related circuitry is shown in FIG. 1A. A preferred pixel configuration of 1082 rows and 1928 columns is shown in FIG. 1D. The transistor portions of the pixels are shown at 211 as integrated circuits in electrical schematic form in FIG. 1A. FIG. 1B is an electrical schematic drawing showing only the transistor portion of a single pixel circuit and the photodiode portion of the pixel, all in schematic form. These integrated pixel circuits are produced in and on a silicon substrate using standard CMOS techniques. The various photodiode portions of each pixel are laid down in continuous layers on top of the integrated circuits and are shown in FIG. 1A as actual layers. Each pixel comprises an impurity-doped diffusion region 130 that is a portion of the reset transistor M.sub.rst and represents a part of the charge collection node 120 as shown in FIG. 1B.

Pixel electrode 116, shown in FIG. 1A is connected to charge collecting node 120. Pixel circuit 211 includes collection capacitor CS, source follower buffer Msf, selection transistor Mrs1 and reset transistor Mrst. Transistor portion 211 uses p-channel transistors for reset transistor Mrst and n-channel transistors for source follower transistor Msf and selection transistor Mrs1. The voltage at COL (out) 256 is proportional to the charge Q(in) stored on the collection capacitor CS. By reading this node twice, once after the exposure to light and once after the reset, the voltage difference is a direct proportional to the amount of light producing charge pairs in the pixel. Transistor portion 211 is referenced to a positive voltage Vcc at node 262 (typically 2.5 to 5 Volts). Pixel circuitry for this array is described in more detail in the '353 patent.

An alternate embodiment is a two-transistor pixel circuit design, where it does not use the source follower transistor Msf in FIG. 1A. Sensors incorporated with this 2-transistor design are called "passive pixel sensor"(PPS). The preferred embodiment, using 3-transistor pixel circuit design, is usually referred as "active pixel sensor" (APS). Compared to the passive pixel sensor, APS has better noise immunity during readout.

Interconnect Structure

The array includes an interconnect structure 115 comprised of dielectric layers providing insulation and electrical interconnections of various elements of the pixel cell array. These interconnections include a set of vias 135 and metalized regions 136 for each pixel connecting diffusion region 130 with patterned electrode pads 116 formed on top of the interconnect structure 115. Interconnect structure 115, with metalized regions 136 and vias 135 are produced using standard CMOS fabrication techniques. In the standard CMOS fabrication process, metal lines are formed of a stack of Titanium Nitride (TiN) and Aluminum layers, where Aluminum lines are stacked on top of TiN lines and TiN is making contact with the vias. Aluminum has very high diffusivity with amorphous silicon; therefore, in this embodiment electrode 116 made of Titanium Nitride without a top Aluminum layer. This technique is an important improvement developed by Applicants to improve sensor performance. Other metals, such as Titanium, Tungsten, Titanium-Tungsten alloy and Tungsten Nitride, can be used as well. But Titanium Nitride is readily available in a typical CMOS process; therefore, it is Applicants' preferred material to prevent diffusion of Aluminum.

Photodiode Layer (For Visible Light Sensor)

FIG. 1A shows a photodiode layer designed for a visible light sensor for a spectral range of about 400 nm to about 900 nm. Each pixel includes an n-i-p photodiode portion formed by continuous layers laid down on top of the interconnect structure 115 and patterned electrode pads 116. In this case the n-i-p photodiode structure is reverse biased with the top electrode 108 at a potential of +3.3 Volts and the collection electron 116 at a potential of about +2.0 Volts at the beginning of each collection cycle as a consequence of the reset voltage VRST being ground (zero Volts). With this configuration positive charges created by photons in the i-layer 112 will flow downward to electrodes 114 to increase the potential on capacitor CS and negative charges will flow upward to electrode 108. (The reader should note here that in some embodiments of the present invention there are advantages in collecting negative charges in the pixels. In this case the reset potential is at a higher voltage than the potential of the top electrode and the layer just below the top electrode is a p-layer and the layer just above the pixel electrode 116 is an n-layer. In referring to these layer diode structures in this application we will read from the top down so that the structure shown in FIG. 1A is an n-i-p structure and the one just described above is a p-i-n structure. In the p-i-n structure the positive charges will flow upward to the top electrode during the charge collecting cycle and the negative charges will flow downward and will be collected on the pixel electrodes reducing the potential of the pixel capacitors.) The lowest of the photodiode layers, p-layer 114, is about 0.01 micron thick and is comprised of p-doped hydrogenated amorphous silicon. This layer preferably also includes carbon at concentrations between about 5 to 35 percent. (Carbon concentrations as high as 50 percent could be used. In prototype devices actually built and tested by Applicants, the carbon concentration was about 30 percent.) Applicants have discovered that carbon doping at this concentration does not significantly adversely affect the quality of this layer as a p-type semiconductor but does substantially increase the electrical resistivity of the layer. This issue is discussed in more detail below. The next higher layer, layer 112 is an intrinsic layer of the n-i-p photodiode region of the array. It is hydrogenated amorphous silicon with no doping and is in this embodiment about 0.5 to 1.0 micron thick. The top photodiode layer 110 is n-doped hydrogenated amorphous silicon and is about 0.005 to 0.01 micron thick. A transparent electrode layer 108 is a layer of indium tin oxide deposited on top of n-layer 108 about 0.06 micron thick. This material is electrically conductive and also transparent to visible light.

Sensor Array Circuitry

A block diagram of the sensor array circuitry for the two millions pixel array is shown in FIG. 1C. In Applicants' design, 1936.times.1090 pixels form the pixel array. This sensor design uses architecture with Column-Parallel Analog-to-Digital conversion (ADC), where each column has its own ADC. For image sensors, typically, the ADC requires 10-bits accuracy. A 10-bit and 60 MHz ADC itself requires the state-of-the-arts design, which may require fabrication processes beyond a typical CMOS based process. Worse than that, it generates a lot of noise and heat that affect the overall sensor performance. In contrast, Column-Parallel ADC can run at the frequency at "line rate" which, in Applicants' two millions pixel sensor, is about a factor of 1000 slower than the pixel rate. This allows Applicants to use much simpler CMOS-process-compatible ADC designs. Because of the slow conversion rate, the noise and heat can be reduced leading to better sensor performance. In FIG. 1C, the timing control and bias generator circuitry on chip generate all the timing clocks and voltages required to operate the on-chip circuitry. They are to simplify the interface between the sensor and other camera electronics, and they allow sensor users to use a single master clock and single supply voltage. These are desirable features in sensor application. In Applicants' two million pixels sensor design, there are two 10-bit video output ports, as shown in FIG. 1C, Dout-Even [9:0] and Dout_Odd [9:0] representing the video output from even columns and odd columns, respectively. Not shown in the figure is an option that allows the sensor users to select an option to use only a single 10-bit port for video output. This single port design allows Applicants to use a smaller chip carrier because at least ten I/O pins can be removed. However, to support the single-port output, Applicants use a switch design that multiplexes the even and odd column video to have the right sequence. This switch needs to operate at higher frequency, and possible higher noise. In some applications, users might want to use the two-port output in order to reduce the noise caused by any elements running at high frequency on chip. For reasons such as these, in Applicants' embodiment the choice of single-port vs. two-ports is an option to sensor users. In Applicants' two-million pixel sensor, a serial I/O port is designed to allow sensor users to read and change some of the parameters for running the sensor. Applicants' two million-pixel sensor has 1928.times.1082 active pixels. As shown in FIG. 1D surrounding the active pixel region are 4 pixel regions covered with visible light shields that can be used as dark reference. FIG. 1E shows Applicants' design to separate the even and odd columns so one set would come from top and one set would come from the bottom. FIG. 1F shows the column-based signal chain of Applicants' two million pixels sensor design. The signal coming out of the pixel region will be held and sampled into the column amplifier circuit. In the design, sensor users are allowed to program the amplification factor depending upon the signal level. The sensor uses other on-chip intelligence to automatically change the amplification factors. At this point, the signal is still analog in nature. Then this signal goes to the column-based ADC to be converted into digital signal. In Applicants design, there are two ADC conversions, one is for the signal and another one is for the reference. Applicants call this technique Delta Double Sampling (DDS). This technique allows Applicants to remove any offset the signal may experience when it passes physically from the pixel region to ADC region. It reduces the fixed pattern noise, commonly a major weakness for CMOS-based Active Pixel Sensor (APS). After DDS, the offset-cancelled digital signal is fetched into the digital signal processing chain, shown in FIG. 1G. FIG. 1H shows a preferred color filter pattern. The signal goes into the Global Offset and Gain Adjustment Circuit (GOGAC) and Dark Reference Average Circuit (DRAC) at the same time. The DRAC circuit calculates the average in the dark reference pixel region, which can provide the signal level representing Dark. In the GOGAC circuit, the gain and offset are applied to the incoming digital signal. After that the digital signal is fetched into the White Balance Offset and Gain Adjustment Circuit (WBOGAC). WBOGAC applies a separate gain and offset according to the color filter the pixel is covered with. The purpose of it is to achieve a white-balanced signal under various light-sources. The parameters can be programmed in by the sensor users or by the on-chip intelligence.

Specifications for Two-Million Pixel Sensor

Applicants have built and tested a prototype two-million pixel sensor as shown in FIGS. 1A through FIG. 11. This sensor is ideally suited for use as a camera for high definition television, cellular phone cameras, surveillance cameras, embedded cameras on portable computers, PDA cameras and digital still cameras. Applicant's specifications for this sensor are summarized below: 1. Photo-sensing layer: a. n-i-p photodiode structure; b. n-i-p is made of hydrogenated amorphous silicon; c. n-i-p layers are un-patterned; d. a surface electrode layer covers over the n-i-p layer structure; e. the surface electrode layer is un-patterned; f. the surface electrode layer is transparent to visible light; g. the surface electrode layer is Indium Tin Oxide (ITO); h. the surface electrode layer is electrically biased to a constant voltage; i. the constant voltage in Item H is around 3.3V; j. a conductive pixel electrode covers substantial area of a said pixel; k. a electrical field is established across the n-i-p layers by applying voltages drop between the surface electrode and metal pixel electrode; l. p-layer is doped with p-type impurity; m. I-layer is un-intentionally doped intrinsic layer; n. n-layer is doped with n-type impurity; o. p-layer is the layer making electrical and physical contact to the conductive pixel electrode and through the pixel electrode to the underlying CMOS pixel circuitry electrically; p. p-layer is very resistive to avoid pixel-to-pixel crosstalk; q. the high resistivity in p-layer is achieved by adding carbon atoms or molecules into P layer; r. Item j is made of metal; s. Item j is made of metallic nitride; t. Item j is made of Titanium Nitride; 2. Pixel Circuitry: a. has an insulating layer, fabricated with the known semiconductor process, between the conductive pixel electrode and underlying pixel circuitry; b. has at least one via, passing through the insulating layer, connecting electrically the said pixel electrode to said underlying pixel circuitry; c. each pixel comprises of a charge collection node, charge sense node, charge storage circuitry, signal reset circuitry and signal readout selection circuitry; d. each pixel circuit comprises of three transistors; e. the gate of one of the transistor is electrically connected to the charge sense node; f. one of the transistor is used for signal reset to a known state; g. one of the transistor is used for signal readout selection; h. Another embodiment is not to use Items (a) and (b) and have the pixel electrode making direct physical and electrical contact to the diffusion area of the reset transistor (Item f). 3. Array Circuitry: a. the sensor array has 2 million pixels; b. each pixel is 5 um.times.5 um; c. the 2 million pixels is formed as 1928 (columns).times.1082 (rows) active area; d. minimum four metal covered pixels, 4 pixels wide, surround the active area; e. the metal covered pixels are used to establish a dark reference for the array; f. each column has an analog-to-digital converter (ADC); g. each column has circuits for signal condition, signal amplification and sample-and-hold; h. the array is arranged to have the signal of even columns and odd columns coming out of from the top and bottom of the array, separately; i. Items F and G are designed to with the width of two pixels wide; j. A delta double sampling (DDS) scheme is used to sample the signal and reference voltages consecutively; k. the sampled signal and reference voltages are converted by the column ADC into digital signals; l. the difference between the said signals in Item k determines the light level detected by the photo-sensing device; m. there are two output data ports, one for even columns and one for odd columns n. the sensor has on-chip circuit to multiplex the even and odd column output to make a pixel-sequential video output through a single port; o. the sensor has on-chip circuit to accept one single voltage input and generates all bias voltages needed to run various circuits on chip; p. the sensor has an option not to use the circuit of Item O but to accept multiple voltage inputs to run various circuits on chip; q. Item G has circuitry providing the selection of multiple signal amplification factors; r. the multiple signal amplification factor covers 1.times. to 8.times., with 256 increments; s. the fine increment of amplification factor is to allow fine adjustment for auto exposure control; t. the sensor array can be covered with color filter; u. the color filters comprises of Red, Green and Blue filters; v. the color filter array is arranged with four pixels as a unit, the upper-left pixel covered with Red filter, the upper-right covered with Green filter, the lower-left covered with Green filter and the lower-right covered with Blue filter; w. there is a timing circuitry on the same chip, which provides all the clocks necessary to operate the pixel and readout circuitry; x. the timing circuitry also provides the synchronization (pixel, line and frame) signals which enables other chips to interface with this image sensor; y. the timing circuitry also provide timing control for light exposure time; z. there are circuits on chip to provide some of the bias voltage to operate other parts of the circuit; aa. the array and pixel circuits are fabricated with CMOS process.

Crosstalk Reduction

With the basic design of the present invention where the photodiode layers are continuous layers covering pixel electrodes, the potential for crosstalk between adjacent pixels is an issue. For example, when one of two adjacent pixels is illuminated with radiation that is much more intense than the radiation received by its neighbor, the electric potential difference between the surface electrode and the pixel electrode of the intensely radiated pixel will become substantially reduced as compared to its less illuminated neighbor. Therefore, there could be a tendency for charges generated in the intensely illuminated pixel to drift over to the neighbor's pixel electrode.

In the case of a three-transistor unit cell design, the photo-generated charge is collected on a capacitor at the unit cell. As this capacitor charges, the voltage at the pixel contact swings from the initial reset voltage to a maximum voltage, which occurs when the capacitor has received its total charge for the charge-collection interval. A typical voltage swing is 1.4V. Due to the continuous nature of Applicant's coating, there is the potential for charge leakage between adjacent pixels when the sense nodes of those pixels are charged to different levels. For example, if a pixel is fully charged and an adjacent pixel is fully discharged, a voltage differential of about 1.4V will exist between them. There is a need to isolate the sense nodes among pixels so crosstalk can be minimized or eliminated.

Gate-Biased Transistor

As explained in Applicant's parent patent application Ser. No. 10/072,637 that has been incorporated herein by reference, a gate-biased transistor can be used to isolate the pixel sense nodes while maintaining all of the pixel electrodes at substantially equal potential so crosstalk is minimized or eliminated. However, an additional transistor in each pixel adds complexity to the pixel circuit and provides an additional means for pixel failure. Therefore, a less complicated means of reducing crosstalk is desirable.

Increased Resistivity in Bottom Photodiode Layer

Applicants have discovered that crosstalk between pixel electrodes can be significantly reduced or almost completely eliminated in preferred embodiments of the present invention through careful control of the design of the bottom photodiode layer without a need for a gate-biased transistor. The key elements necessary for the control of pixel crosstalk are the spacing between pixel contacts and the thickness and resistivity of the photodiode layers. These elements are simultaneously optimized to control the pixel crosstalk, while maintaining all other sensor performance parameters within desired ranges. The key issues related to each variation are described below.

1. Pixel Contact Spacing

Increased spacing, l, between pixel contacts increases the effective resistance between the pixels, as described in the relationship between resistance and resistivity.

.rho..times..times..times. ##EQU00001##

The spacing between pixel contacts is a consequence of the designed pixel pitch and pixel contact area. From the geometric configuration alone, we can create a differentiation so carriers would favor one direction over the other. For example, along the vertical direction, the resistance becomes R.sub.v, =.rho..times.T/(W.times.L), where .rho. is the resistivity, T is the p-layer thickness, W is the pixel width and L is the pixel length.

In most cases W=L, therefore, we can get R.sub.v=.rho..times.T/W.sup.2 On the other hand, along the lateral direction, the resistance becomes R.sub.1=.rho./T. The resistance ratio between lateral and vertical is R.sub.1/R.sub.v=(W/T).sup.2

This can create a preferred carrier flow direction, favorable in vertical direction, as long as W/T>1. In Applicants' practice, the p-layer thickness is around 0.01 um and pixel width is about 5 um, W/T=500 which is much greater than 1. Of course, the final pixel contact size must be selected based on simultaneous optimization of all sensor performance parameters.

2. Layer Thickness

Decreasing the coating thickness, t, results in an increase in the effective inter-pixel resistance as described in equation 1. In the case of an amorphous silicon n-i-p diode, the layer in question is the bottom p-layer. In the case of an amorphous silicon p-i-n diode, it is the bottom n-layer. In both cases, only the bottom doped layer is considered because the potential barriers that occur at the junctions with the i-layer prevent significant leakage of collected charge back into the i-layer. Also in both cases, there is a practical limit to the minimum layer thickness, beyond which the junction quality is degraded.

3. Coating Resistivity

The parameter in Equation 1 that allows the largest variation in the effective resistance is .rho., the resistivity of the bottom layer. This parameter can be varied over several orders of magnitude by varying the chemical composition of the layer in question. In the case of the amorphous silicon N-layer and P-layer discussed above, the resistivity is controlled by alloying the doped amorphous silicon with carbon and/or varying the dopant concentration. The resulting doped P-layer or N-layer film can be fabricated with resistivity ranging from 100 .OMEGA.-cm to more than 10.sup.11 .OMEGA.-cm. The incorporation of a very high-resistivity doped layer in an amorphous silicon photodiode might decreases the electric field strength within the I-layer, therefore whole sensor performance must be considered when optimizing the bottom doped layer resistivity.

Carbon Preferred for Increased Resistivity

The growth of a high-resistivity amorphous silicon based film can be achieved by alloying the silicon with another material resulting in a wider band gap and thus higher resistivity. It is also necessary that the material not act as a dopant providing free carriers within the alloy. The elements known to alloy with amorphous silicon are germanium, tin, oxygen, nitrogen and carbon. Of these, alloys of germanium and tin result in a narrowed band gap and alloys of oxygen, nitrogen and carbon result in a widened band gap. Alloying of amorphous silicon with oxygen and nitrogen result in very resistive, insulating materials. However, silicon-carbon alloys allow controlled increase of resistivity as a function of the amount of incorporated carbon. Furthermore, silicon-carbon alloy can be doped both n-type and p-type by use of phosphorus and boron, respectively.

Amorphous silicon based films are typically grown by plasma enhanced chemical vapor deposition (PECVD). In this deposition process the film constituents are supplied through feedstock gasses that are decomposed by means of a low-power plasma. Silane or di-silane are typically used for silicon feedstock gasses. The carbon for silicon-carbon alloys is typically provided through the use of methane gas, however ethylene, xylene, dimethyl-silane (DMS) and trimethyl-silane (TMS) have also been used to varying degrees of success. Doping may be introduced by means of phosphene or diborane gases.

Preferred Process for Making Photodiode Layers

In Applicants' current practice for a n-i-p diode layer structure, the p-layer, which is making contact with the pixel electrode, has a thickness of about 0.01 microns. The pixel size is 5 microns.times.5 microns. Because of the aspect ratio between the thickness and pixel width (or length) is much smaller than 1, within the P-layer the resistance along the lateral (along the pixel width/length direction) is substantially higher than the vertical direction, based upon Equation 1. Because of this, the electrical carriers prefer to flow in the vertical direction than in the lateral direction. This alone may not be sufficient to ensure that the crosstalk is low enough. Therefore, Applicants prefer to increase the resistivity by introducing carbon atoms into p-layer to make it become a wider band-gap material. Our preferred p-layer is a hydrogenated amorphous silicon layer with carbon concentration about 10.sup.22 atoms/cc. The hydrogen content in this layer is in the order of 10.sup.21-10.sup.22 atoms/cc, and the p-type impurity (Boron) concentration in the order of 10.sup.20-10.sup.21 atoms/cc. This results in a film resistivity of about 10.sup.10 ohm-cm. For a 5-micron.times.5-micron pixel, we have found out that negligible pixel crosstalk can be achieved even when the p-layer resistivity is down to about 2-3.times.10.sup.7 ohm-cm. Like what is described above, there is a need of engineering trade-offs among p-layer thickness, carbon concentration, boron concentration and pixel size to achieve the required overall sensor performance. Therefore, the resistivity requirement may vary for other pixel sizes and configurations. For this n-i-p diode with 5-micron.times.5-micron pixel, our I-layer is an intrinsic hydrogenated amorphous silicon with a thickness about 0.5-1 micron. The n-layer is also a hydrogenated amorphous silicon layer with n-type impurity (Phosphorous) concentration in the order of 10.sup.20 to 10.sup.21 atoms/cc.

For applications where the polarity of the photodiode layers are reversed and the n-layer is adjacent to the pixel electrode, the carbon atoms/molecules are added to the n-layer to reduce crosstalk.

The Physics of Continuous Photodiode Layer Structures

Layered photodiode structures of the type shown in FIG. 1A have great practical advantages over conventional crystalline photodiode structures that are either grown epitaxially on CMOS readout arrays, or bump bonded to CMOS readout arrays. Crystalline photodiode structures, such as crystalline silicon, for example, feature a perfectly periodic spacing of atoms with very few impurities or crystal dislocations. These structures may be mathematically modeled. According to models typically utilized, energy potential of each atom, combined with a wave function representation of the mobile charges, results in an energy band gap between the valence and conduction bands. Incident photons provide the energy to elevate the electron energy from the valence band to the conduction band, thereby creating mobile charges. The near perfect order of the crystalline semiconductor, and relative absence of impurities or dislocations, results in a very low density of states in the energy band gap and a high mobility of charges. The addition of p and n dopant layers provides p-i-n or p-n photodiode structures with spatial depletion regions that permit electrical separation of liberated pairs produced by incident photons. This enables efficient light detection of light at wavelengths .lamda..sub.B corresponding to photon energies above the band gap energy E.sub.B. That is .lamda..sub.B<hc/E.sub.B, where h is Planck's constant and c is the speed of light. The band gap also enables suppression of thermally generated dark noise that ultimately limits the imaging performance.

An amorphous p-i-n photodiode structure fabricated from hydrogenated amorphous silicon (a-Si:H) has similar light absorption properties as a crystalline p-i-n photodiode. The amorphous p, i and n layers feature a disordered, but somewhat periodic, spacing of the silicon atoms; these atoms are surrounded by a plurality of hydrogen atoms. The bulk semiconductor properties arise from averaging the microscopic features of the photodiode structure over the effective photon detection width x of an incident photon (where x=1.22 .lamda.f# where f# is the f-number of the optical system and .lamda. is the wavelength of the incident photon). This value x=1.22 .lamda.f# is hereinafter referred to as the effective photon width. The periodicity of the silicon atoms in the amorphous photodiode has enough definition over the distance x so that the photon essentially sees a semiconductor material with a forbidden energy bandgap separating conduction and valence bands, and a spatial depletion region primarily in the i-layer. The forbidden energy bandgap in an amorphous material tends to feature a much larger density of energy states than in a crystalline semiconductor material due to the amorphous nature of the material. This leads to increased dark current and lower mobility of charges in an amorphous photodiode material. However, the density of states can be controlled in an amorphous material so that the achievable image performance is limited by the CMOS readout array on which the amorphous photodiode structure is applied.

The major practical advantage of amorphous photodiode structures involves the elastic nature of amorphous materials. Amorphous materials, such as amorphous silicon, can gracefully incur much larger stresses because the silicon atoms are imbedded in a sea of hydrogen atoms; the hydrogen bonds provide material elasticity that enables the amorphous materials to be coated on material varying (i.e. metal pixel pads separated by silicon dioxide insulator, for example) or even topologically varying CMOS readout arrays. In comparison, crystalline materials, fabricated using molecular beam epitaxy (MBE), require precise lattice matching to a flat underlying crystalline substrate, in order to minimize the interface stress.

Microcrystalline photodiode structures, such as a microcrystalline silicon p-i-n photodiode, for example, feature very small (10-100 nm) crystal structures imbedded in amorphous material layers in a disordered fashion. The average size of the microcrystallites, determined by the coating parameters, is much smaller than the photon wavelength, the effective photon width x, and the pixel size of the CMOS readout array. The semiconductor properties of microcrystalline photodiodes, such as dark current and charge mobility, are primarily determined by the impurities and dislocations along the grain boundaries of the micro-crystallites. The microcrystalline values of dark current and charge mobility typically lie between published values of dark current and charge mobility of the amorphous and crystalline materials making up the microcrystalline material. As a natural extension of this simple p-i-n photodiode structure, the intrinsic layer can be comprised of one intrinsic amorphous silicon layer and one intrinsic microcrystalline silicon layer. This composite-intrinsic layer allows a sensor to utilize the efficient light sensing to visible spectrum by amorphous silicon layer and the efficient light sensing to near IR spectrum by microcrystalline silicon.

By coating the amorphous or microcrystalline photodiode structure over the CMOS readout circuitry, the resulting sensor has a near-unity fill factor. This feature potentially results in near unity quantum efficiency for a specific wavelength band. This provides a distinct advantage over a front-illuminated charge-coupled device (CCD) or conventional CMOS imagers, both which effectively shield a large portion of the pixel's active photo-converter area with overlying readout circuitry.

Various Types of Photodiode Layer Structures

The present invention provides the opportunity to tailor the spectral response of sensor arrays to various desired spectral ranges by appropriate choice of the material used for the layers making up the continuous photodiode layer structure shown for example as photodiode layer structure 122 in FIG. 1A. Four of these preferred layer structures are described in detail below. Three of these structures provide responses in the near infrared. Techniques are also described for modifying each of the four structures to expand the spectral range into the ultraviolet spectral range.

Amorphous Silicon Photodiode

In the first preferred embodiment of the present invention, the photodiode layers are n-i-p layers comprised of hydrogenated amorphous silicon (a-Si:H). They are applied over the pixelated surface of a CMOS readout array that has been designed to provide electrical contact to the photodiode at each pixel. In this embodiment the photodiode is operated with a -1 V reverse bias voltage to provide an enhanced electric field across the i-layer to allow efficient collection of photo-generated charge.

The a-Si:H photodiode structures is fabricated using by plasma enhanced chemical vapor deposition. In this process, feedstock gases are delivered to a vacuum chamber and dissociated by means of radio frequency plasma. Once the gases are broken down, the resulting radicals react at all exposed surfaces, resulting in film growth. The first deposited layer is a p-type impurity doped layer that is produced using silane (SiH.sub.4) gas with a small addition of boron; this p-layer is typically 50-700 angstroms thick. The next deposited layer that is the intrinsic amorphous silicon i-layer that primarily incorporates silane gas; this i-layer is typically 0.5-1 micron thick. The third deposited layer is an n-type impurity doped layer that combines silane gas with a small addition of phosphorus; this n-layer is typically 50-700 angstroms thick. An indium-tin oxide (ITO) top electrode layer is deposited on the n-layer to provide the conductive top surface to apply the electric bias field. The ITO material is transparent in the infrared and visible spectral energy but becomes increasingly absorptive as wavelength is decreased into the ultraviolet spectrum.

The p-i-n photodiode structure is designed to collect positive charges (holes) at the pixel pad and electrons at the top ITO electrode. The quantum efficiency (QE) versus wavelength, and the absorption depth versus wavelength, for a-Si:H are displayed in FIG. 2 and FIG. 3. The a-Si:H photodiode has neglible photoresponse for wavelengths larger than 750 nm due to the 1.7 eV bandgap energy of the a-Si:H i-layer. The absorption depth of the i-layer grows quickly for photon energies that are smaller than the bandgap energy, and therefore becomes much larger than the i-layer thickness for wavelengths larger than 750 nm.

Microcrystalline Silicon Photodiode

In order to extend the photoresponse to wavelengths larger than 750 nm, a microcrystalline silicon i-layer can be substituted for the a-Si:H i-layer. Amorphous silicon has a 1.7 eV bandgap which limits photoresponse for wavelengths above 750 nm. In contrast, crystalline silicon has a bandgap of 1.1 eV which permits photon detection to 1100 nm wavelengths. Microcrystalline silicon can have an effective bandgap anywhere in the range of 1.7 eV to 1.1 eV, depending on the degree of crystallinity. FIG. 4 shows microcrystalline silicon can even absorb photons with energies below the 1.1 ev band-gap energy of crystalline silicon. Therefore, the substitution of .mu.c-Si for a-Si in the i-layer enables photoresponse to wavelengths slightly beyond 1100 nm. The reduction in band gap occurs because of a continuous change in character, from amorphous silicon to crystalline silicon as the degree of crystallinity increases. Concurrently, the absorption coefficient decreases with increasing crystallinity as the material transitions from the direct band gap of amorphous silicon to the indirect band gap of crystalline silicon. However, the absorption depth of .mu.c-Si remains significantly larger than crystalline silicon over the entire absorption range.

The microcrystalline i-layer also features a photoresponse time constant that is substantially faster than amorphous silicon due to the increased mobility of the charge carriers in microcrystalline silicon. When a light signal is removed from an amorphous silicon photodiode structure, the response of the photodiode does not instantaneously drop to zero. Rather, there is a decay in the signal with a time constant on the order of 100-300 microseconds. This time constant is unnoticeable for 30 Hz video sensors with a 33 millisecond integration time per frame. However, this time constant does limit the extension of this sensor technology to faster frame rates, such as 1 kHz frame rate sensors, for example. Due to the lower density of states in the more orderly microcrystalline materials, the time constant for this decay could be reduced to as low as 1 microsecond.

Sensors with microcrystalline silicon photoconductor layers covering active pixels have several distinct advantages over traditional crystalline silicon sensors. One advantage is that the photo-detector is grown as a continuous film on the surface of a CMOS readout array so that the entire surface area of the imaging array is utilized for light detection, resulting in a 100% fill factor. The second advantage arises as a result of the absorption coefficient of .mu.c-Si as compared to crystalline silicon. As shown in FIG. 4, the absorption coefficient of .mu.c-Si is significantly higher than crystalline silicon over the entire absorption range. Additionally, the absorption of .mu.c-Si extends slightly farther into the infrared than crystalline silicon. The third advantage arises as a result of using a p-i-n or n-i-p diode structure instead of the p-n structure used in prior art crystalline silicon devices. In a crystalline silicon p-n diode, the silicon wafer is used as the absorbing layer of the photo-detector. In this configuration, the electric field is generated at the p-n interface, and as stated above, only extends about a micron into the crystalline silicon diode. Infrared light penetrates tens of microns into the crystalline silicon. At this depth, there is no electric field to assist in collection. As a result, diffusion is relied on for collection. With no field, the charges when generated will randomly diffuse in all directions. This results in the loss of the half of the charges that drift downward, away from the electronics. Of the remaining charges, only a few will drift directly upward to the pixel into which the light entered. The remaining charges will either recombine or will migrate into adjacent pixels, resulting in significant cross talk. As a result the pixel in this type of infrared sensor must be kept sufficiently large to keep cross talk under control. In contrast, in the p-i-n or n-i-p device, the electric field is applied across the i-layer. This develops a vertical field across the i-layer that causes virtually all substantial charges generated in the i-layer to drift and be collected in pixel in which they were generated. This allows use of much smaller pixels.

A review of the literature shows that .mu.c-Si is very promising for use in these structures. Sensitivity to 1-micron wavelength and beyond has been reported by many groups. The .mu.c-Si layer can be grown by several methods, however the use of RF PECVD is directly compatible with current processing and so is Applicants' preferred method.

Internal research conducted by Applicants has confirmed the shift in the absorption spectrum of .mu.c-Si as compared to a-Si microcrystalline silicon photodiode structure. The absorption spectrum of the layers are compared in FIG. 5. After development of a .mu.c-Si i-layer, a full p-i-n photodiode structure was fabricated by Applicants and their fellow workers. The quantum efficiency as a function of wavelength for this device is shown in FIG. 6.

Microcrystalline Copper Indium Diselenide

Another preferred embodiment of the present invention for a near infrared image sensor is a copper indium diselenide/cadmium sulfide (CIS/CdS) photodiode structure. FIG. 2 shows that the photo-response of this photodiode structure extends over the visible spectrum into the near infrared spectrum. The development of CIS/CdS photodiode structure by the solar cell industry has led to a technology with the highest power conversion efficiency to date, primarily because the sensitivity of this structure spans a much wider range of the solar spectrum (350 nm-1250 nm).

A preferred method for fabricating a CIS/CdS photodiode structure first involves the deposition of a copper indium gallium diselenide (CIGS) layer. This layer is preferably about 1-2 microns thick and is deposited using a four crucible evaporative coating process. Each of the four crucibles contains one of the four constituent elements and is elevated to a temperature to produce a vapor pressure of the constituents to provide the correct stoichiometric ratio in the CIGS layer. The preferred stoichiometric ratios are 22-24% Cu, 50% Se, and the balance being In and Ga with a Ga/In plus Ga ratio of 0.2 to 0.3. The preferred substrate temperature is 400-450 degrees C.; this temperature is lower than the con