Wiring graphic verification method, program and apparatus Number:7,120,881 from the United States Patent and Trademark Office (PTO) owispatent An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.<H verification, apparatus, Wiring, graphic, , 7120881.html, Patent, pto, 7120881

Title: Wiring graphic verification method, program and apparatus

Abstract: An edge extraction unit extracts vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics, and a wiring width classification unit executes a scaling process for the overall wiring graphics to classify the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width. A vertical and horizontal wiring edge extraction unit extracts the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges, and a vertical and horizontal wiring interval verification unit verifies intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range. A slanted wiring edge extraction unit extracts slanted wiring edges which are in contact with graphics classified into the wiring width ranges, and a slanted wiring interval verification unit verifies intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

Patent Number: 7,120,881 Issued on 10/10/2006 to Kodama, et al.

Inventors: Kodama; Chikaaki (Kasukabe, JP), Yoshitake; Akiihiro (Kawasaki, JP)
Assignee: Fujitsu Limited (Kawasaki, JP)

Appl. No.: 10/805,478

Filed: March 22, 2004

Foreign Application Priority Data


Apr 11, 2003 [JP]			2003-107522

Current U.S. Class: 716/5

Current International Class: G06F 17/50 (20060101)

Field of Search: 716/5

References Cited [Referenced By]

U.S. Patent Documents


6427225	July 2002	Kitada et al.
6941531	September 2005	Teig et al.
2002/0049957	April 2002	Hosono et al.
2004/0205683	October 2004	Kovacs-Birkas et al.
2006/0080634	April 2006	Beale

Foreign Patent Documents


8-55140	Feb., 1993	JP
11-96200	Apr., 1999	JP
2001-13673	Jan., 2001	JP

Primary Examiner: Dinh; Paul
Assistant Examiner: Parihar; Suchin
Attorney, Agent or Firm: Staas & Halsey LLP

Claims

What is claimed is:

1. A computer-aided wiring graphic verification method for verifying wiring intervals in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for a circuit design, the method comprising: an edge extraction step, by an edge extraction unit, extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step, by a wiring width classification unit, executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction step, by a vertical and horizontal wiring edge extraction unit, extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges; a vertical and horizontal wiring interval verification step, by a vertical and horizontal wiring interval verification unit, verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction step, by a slanted wiring edge extraction unit, extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and a slanted wiring interval verification step, by a slanted wiring interval verification unit, verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

2. The wiring graphic verification method according to claim 1, wherein the wiring width classification step includes setting one or more reference wiring widths for defining the wiring width ranges for each of the vertical and horizontal wiring and the slanted wiring.

3. The wiring graphic verification method according to claim 1, wherein the wiring width classification step includes, if a single reference wiring width is set for defining the wiring width ranges, executing a reduction process for the overall wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the reference width to disappear wiring graphics not greater than the reference wiring width, and thereafter executing an enlargement process which moves vertex coordinates of remaining wiring graphics toward outside of the graphic by one-half of the reference wiring width, to thereby perform classification into the wiring graphics not greater than the reference wiring width and the wiring graphics greater than the reference wiring width.

4. The wiring graphic verification method according to claim 1, wherein the wiring width classification step includes, if a plurality of reference wiring widths are set for defining the wiring width ranges, selecting the reference wiring width in ascending order or descending order, and repeating the process which includes, executing a reduction process for the wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the selected reference wiring width to disappear wiring graphics not greater than the reference value, and thereafter executing an enlargement process which moves vertex coordinates of remaining graphics toward outside of the graphic by one-half of the reference wiring width, to thereby perform classification into the wiring graphics not greater than the reference wiring width and the wiring graphics greater than the reference wiring width.

5. The wiring graphic verification method according to claim 1, wherein the vertical and horizontal wiring width verification step includes verifying whether or not the wiring intervals to the edges of vertical and horizontal wiring graphics opposed to the vertical and horizontal wiring edges violate the reference interval of the vertical and horizontal wiring.

6. The wiring graphic verification method according to claim 5, wherein the slanted wiring width verification step includes verifying whether or not the wiring intervals to the edges of slanted wiring graphics which are located in orthogonal direction to the vertical and horizontal wiring edges toward outside of the graphics violate the reference interval of the vertical and horizontal wiring.

7. The wiring graphic verification method according to claim 1, wherein the slanted wiring width verification step includes verifying whether or not the wiring intervals to the edges of slanted wiring graphics opposed to the slanted wiring edges violate the reference interval of the slanted wiring.

8. The wiring graphic verification method according to claim 7, wherein the slanted wiring width verification step includes verifying whether or not the wiring intervals to the edges of vertical and horizontal wiring graphics which are located in orthogonal direction to the slanted wiring edges violate the reference interval of the slanted wiring.

9. The wiring graphic verification method according to claim 1, wherein the slanted wiring graphics are arranged at a slant of 45 degrees relative to the vertical and horizontal directions.

10. The wiring graphic verification method according to claim 1, wherein each of the steps is processed sequentially for each wiring layer.

11. A computer-aided wiring graphic verification method for verifying wiring intervals and wiring widths in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the method comprising: an edge extraction step, by an edge extraction unit, extraction vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step, by a wiring width classification unit, executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction step, by a vertical and horizontal wiring edge extraction unit, extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges; a vertical and horizontal wiring interval verification step, by a vertical and horizontal wiring interval verification unit, verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction step, by a slanted wiring edge extraction unit, extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; a slanted wiring interval verification step, by a slanted wiring interval verification unit, verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range; a minimum wiring width extraction step, by a minimum wiring width extraction unit, extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics; a minimum wiring width verification step, by a minimum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring with errors; a maximum wiring width extraction step, by a maximum wiring width extraction unit, extraction wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and a maximum wiring width verification step, by a maximum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

12. A program stored on a computer readable storage for allowing a computer to execute: an edge extraction step extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction step extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges; a vertical and horizontal wiring interval verification step verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction step extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and a slanted wiring interval verification step verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

13. A program stored on a computer readable storage for allowing a computer to execute: an edge extraction step extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction step extracting the vertical and horizontal wiring edges which are in contact with graphic classified into the wiring width ranges; a vertical and horizontal wiring interval verification step verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction step extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; a slanted wiring interval verification step verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range; a minimum wiring width extraction step extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics; a minimum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring width errors; a maximum wiring width extraction step extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and a maximum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

14. A computer-aided wiring graphic verification apparatus for verifying wiring intervals in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for a circuit design, the apparatus comprising: an edge extraction unit extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification unit executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction unit extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges; a vertical and horizontal wiring interval verification unit verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction unit extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and a slanted wiring interval verification unit verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

15. A computer-aided wiring graphic verification apparatus for verifying wiring intervals and wiring widths in wiring graphic data for wiring masks including vertical and horizontal wirings and slanted wirings created from layout data for semiconductor integrated circuit designing, the apparatus comprising: an edge extraction unit extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification unit executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction unit extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges; a vertical and horizontal wiring interval verification unit verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction unit extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; a slanted wiring interval verification unit verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range; a minimum wiring width extraction unit extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics; a minimum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, the minimum wiring width verification unit outputting minimum wiring width errors; a maximum wiring width extraction unit extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and a maximum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, the maximum wiring width verification unit outputting maximum wiring width errors.

Description

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates generally to a computer-aided wiring graphic verification method, program and apparatus for verifying wiring graphic data for wiring masks created from layout data for circuit design of a large-scale semiconductor integrated circuit, etc., and more particularly to a wiring graphic verification method, program and apparatus for verifying wiring intervals and wiring widths of vertical and horizontal wiring and slanted wiring mixed in the wiring graphic data.

2. Description of the Related Arts

Traditionally, in computer-aided large scale semiconductor integrated circuits design work, a location of devices is determined on the integrated circuit according to a logic circuit diagram or an electronic circuit diagram referred to as a wiring location design of a layout design, and after wiring paths between these devices are determined, a plotting operation for generating mask based on this is performed.

As is well known, in layout design, layout verification is performed. This layout verification is to confirm accuracy of design of plot data (artwork data) for generating mask in final design stage.

In this layout verification, the verification called design rule check (DRC) is performed. This is an operation which verifies that the plot data does not violate geometrical design rules which is designed with various constraint obtained after examining fabrication processes, or the design rules.

In conventional design rule check, it is verified that intervals between wiring graphics and wiring widths do not violate the design rules. In verification of intervals between wiring graphics, verification reference values vary according to the wiring widths. Also, acceptable minimum wiring width and maximum wiring width are defined for each wiring layer.

In verification of wiring intervals targeting the conventional vertical and horizontal wiring, there are a method that extracts wiring graphics which are to be verification targets and checks intervals between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges. Also, for verification of wiring widths, there are a method that extracts wiring graphics which are to be verification targets and checks widths between the wiring graphics and a method that extracts edges between wirings which are to be verification targets and checks intervals between these edges (See Japanese Patent Application Laid-open Pub. Nos. 2001-13673, Hei8-55140 and Hei11-96200).

By the way, in conventional layout design, wiring patterns are arranged in horizontal and vertical directions, but in recent years, slanted wiring in which wiring patterns are arranged in 45 degrees slanted direction has been introduced in order to shorten wiring paths, reduce line resistance and stray capacitance and improve transmission properties associated with higher frequency.

However, in verification of the layout design in case that the vertical and horizontal wiring and the slanted wiring are mixed, if the design reference values for the wiring intervals of the vertical and horizontal wiring and the slanted wiring are different respectively and also if the design reference values for minimum wiring widths and maximum wiring widths of the vertical and horizontal wiring and the slanted wiring are different respectively, then a problem occurs, in which so-called pseudo-errors, which is output as error even when it is not error, is generated by mutual interferences of different design reference values.

In other words, if layout verification is performed according to the design reference value of the vertical and horizontal wiring, the design reference value of the vertical and horizontal wiring is also applied to the slanted wiring and the pseudo-errors is generated. Conversely, if layout verification is performed according to the design reference value of the slanted wiring, the design reference value of the slanted wiring is also applied to the vertical and horizontal wiring and the pseudo-errors is generated.

Therefore, layout verification can not accommodate the layout verification in which the design reference values of the vertical and horizontal wiring and the slanted wiring are different, and different design reference values can not be applied to the vertical and horizontal wiring and the slanted wiring, so the problem occurs, in which the degree of freedom of the layout design is limited.

SUMMARY OF THE INVENTION

It is therefore the object of the present invention to provide a wiring graphic verification method, program and apparatus which enable the layout verification corresponding to different design reference values without generating pseudo-errors, for the wiring graphics in which are mixed the vertical and horizontal wiring and the slanted wiring with different design standards.

(Verification of Wiring Intervals)

In order to achieve the above object, according to a first aspect of the present invention there is provided a computer-aided wiring graphic verification method for verifying wiring intervals in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for a semiconductor integrated circuit designing, the method comprising:

an edge extraction step, by an edge extraction unit, extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a wiring width classification step, by a wiring width classification unit, executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width;

a vertical and horizontal wiring edge extraction step, by a vertical and horizontal wiring edge extraction unit, extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification step, by a vertical and horizontal wiring interval verification unit, verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range; a slanted wiring edge extraction step, by a slanted wiring edge extraction unit, extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and

a slanted wiring interval verification step, by a slanted wiring interval verification unit, verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

In this way, in the wiring graphic verification method of the invention, first, the vertical and horizontal edges and the slanted edges are extracted from the overall wiring graphics in which the vertical and horizontal wiring and the slanted wiring are mixed, and are classified into wiring width ranges by performing the scaling process to the overall wiring graphics, then, by extracting one which contact with the wiring graphics after the scaling process out of previously extracted vertical and horizontal edges and slanted edges, it is possible to individually verify the wiring intervals of the vertical and horizontal wiring and the slanted wiring, with different design reference values, without generating pseudo-errors.

The wiring width classification step may include setting one or more reference wiring widths for defining the wiring width ranges for each of the vertical and horizontal wiring and the slanted wiring.

The wiring width classification step may include, if a single reference wiring width is set for defining the wiring width ranges, executing a reduction process for the overall wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the reference width to disappear wiring graphics not greater than the reference wiring width, and thereafter executing an enlargement process which moves vertex coordinates of remaining wiring graphics toward outside of the graphic by one-half of the reference wiring width, to thereby perform classification into the wiring graphics not greater than the reference wiring width and the wiring graphics greater than the reference wiring width.

The wiring width classification step may include, if a plurality of reference wiring widths are set for defining the wiring width ranges, selecting the reference wiring width in ascending order or descending order, and repeating the process which includes executing a reduction process for the wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the selected reference wiring width to disappear wiring graphics not greater than the reference value, and thereafter executing an enlargement process which moves vertex coordinates of remaining graphics toward outside of the graphic by one-half of the reference wiring width, to thereby perform classification into the wiring graphics not greater than the reference wiring width and the wiring graphics greater than the reference wiring width.

The vertical and horizontal wiring width verification step may include verifying whether or not the wiring intervals to the edges of vertical and horizontal wiring graphics opposed to the vertical and horizontal wiring edges violate the reference interval of the vertical and horizontal wiring. This is verification of the wiring interval between the vertical and horizontal wirings.

The slanted wiring width verification step may include verifying whether or not the wiring intervals to the edges of slanted wiring graphics which are located in orthogonal direction to the vertical and horizontal wiring edges toward outside of the graphics violate the reference interval of the vertical and horizontal wiring. This is verification of the wiring interval with the slanted wiring from the viewpoint of the vertical and horizontal wiring, which is verified with the reference interval of the vertical and horizontal wiring.

The slanted wiring width verification step may include verifying whether or not the wiring intervals to the edges of slanted wiring graphics opposed to the slanted wiring edges violate the reference interval of the slanted wiring. This is verification of the wiring interval between the slanted wirings.

The slanted wiring width verification step may include verifying whether or not the wiring intervals to the edges of vertical and horizontal wiring graphics which are located in orthogonal direction to the slanted wiring edges violate the reference interval of the slanted wiring. This is verification of the wiring interval to the vertical and horizontal wiring from the viewpoint of the slanted wiring, which is verified with the reference interval of the slanted wiring.

(Verification of Wiring Widths)

In order to achieve the above object, according to a second aspect of the present invention there is provided a computer-aided wiring graphic verification method for verifying the wiring width in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the method comprising:

an edge extraction step, by an edge extraction unit, extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a minimum wiring width extraction step, by a minimum wiring width extraction unit, extracting wiring graphics less than predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification step, by a minimum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring width errors;

a maximum wiring width extraction step, by a maximum wiring width extraction unit, extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification step, by a maximum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

In this way, in the wiring graphic verification method targeting the wiring width, first, the vertical and horizontal edges and the slanted edges are extracted from the overall wiring graphics in which the vertical and horizontal wiring and the slanted wiring are mixed, and the wiring graphics less than minimum wiring width and the wiring graphics greater than maximum wiring width are extracted by performing the scaling process to the overall wiring graphics, then, by extracting one which contact with the wiring graphics after the scaling process out of previously extracted vertical and horizontal edges and slanted edges, it is possible to individually verify the minimum wiring width violations and the maximum wiring width violations for the vertical and horizontal wiring and the slanted wiring respectively, without generating pseudo-errors.

The minimum wiring width extraction step may include executing a reduction process for the overall wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the minimum wiring width to disappear wiring graphics less than the minimum wiring width, and thereafter executing an enlargement process which moves vertex coordinates of remaining wiring graphics toward outside of the graphic by one-half of the minimum wiring width, to extract graphics from which wiring graphics not greater than the minimum wiring width are eliminated, and removing the extracted graphics from the overall wiring graphics, to thereby extract wiring graphics less than the minimum wiring width.

The maximum wiring width extraction step may include executing a reduction process for the overall wiring graphics which moves vertex coordinates toward inside of the graphic by one-half of the maximum wiring width to disappear wiring graphics less than the maximum wiring width, and thereafter executing an enlargement process which moves vertex coordinates of remaining wiring graphics toward outside of the graphic by one-half of the minimum wiring width, to thereby extract wiring graphics greater than the maximum wiring.

The slanted wiring graphics may be arranged at a slant of 45 degrees relative to the vertical and horizontal directions. Each of the steps may be processed sequentially for each wiring layer.

In order to attain the above object, according to a third aspect of the present invention there is provided a computer-aided wiring graphic verification method for verifying both wiring intervals and wiring widths in wiring graphic data for wiring masks including vertical and horizontal wirings and slanted wirings created from layout data for semiconductor integrated circuit designing, the method comprising:

an edge extraction step, by an edge extraction unit, extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step, by a wiring width classification unit, executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width; a vertical and horizontal wiring edge extraction step, by a vertical and horizontal wiring edge extraction unit, extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification step, by a vertical and horizontal wiring interval verification unit, verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range;

a slanted wiring edge extraction step, by a slanted wiring edge extraction unit, extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges;

a slanted wiring interval verification step, by a slanted wiring interval verification unit, verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range;

a minimum wiring width extraction step, by a minimum wiring width extraction unit, extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification step, by a minimum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring width errors;

a maximum wiring width extraction step, by a maximum wiring width extraction unit, extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification step, by a maximum wiring width verification unit, extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

(Program)

In order to attain the above object, according to a fourth aspect of the present invention there is provided a computer-executed program for verifying wiring intervals in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the program allowing a computer to execute:

an edge extraction step extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a wiring width classification step executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width;

a vertical and horizontal wiring edge extraction step extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification step verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range;

a slanted wiring edge extraction step extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and

a slanted wiring interval verification step verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

In order to attain the above object, according to a fifth aspect of the present invention there is provided a computer-executed program for verifying wiring widths in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the program allowing a computer to execute:

an edge extraction step extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a minimum wiring width extraction step extracting wiring graphics less than predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring width errors;

a maximum wiring width extraction step extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

In order to attain the above object, according to a sixth aspect of the present invention there is provided a computer-executed program for verifying wiring intervals and wiring widths in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the program allowing a computer to execute:

an edge extraction step extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics; a wiring width classification step executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width;

a vertical and horizontal wiring edge extraction step extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification step verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range;

a slanted wiring edge extraction step extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges;

a slanted wiring interval verification step verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range;

a minimum wiring width extraction step extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, and outputting minimum wiring width errors;

a maximum wiring width extraction step extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification step extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, and outputting maximum wiring width errors.

(Apparatus)

In order to attain the above object, according to a seventh aspect of the present invention there is provided a computer-aided wiring graphic verification apparatus for verifying wiring intervals in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the apparatus comprising:

an edge extraction unit extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a wiring width classification unit executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width;

a vertical and horizontal wiring edge extraction unit extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification unit verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range;

a slanted wiring edge extraction unit extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges; and

a slanted wiring interval verification unit verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range.

In order to attain the above object, according to an eighth aspect of the present invention there is provided a computer-aided wiring graphic verification apparatus for verifying wiring widths in wiring graphic data for wiring masks including vertical and horizontal wiring and slanted wiring created from layout data for semiconductor integrated circuit designing, the apparatus comprising:

an edge extraction unit extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a minimum wiring width extraction unit extracting wiring graphics less than predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, the minimum wiring width verification unit outputting minimum wiring width errors;

a maximum wiring width extraction unit, extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, the maximum wiring width verification unit outputting maximum wiring width errors.

In order to attain the above object, according to a ninth aspect of the present invention there is provided a computer-aided wiring graphic verification apparatus for verifying both the wiring intervals and wiring widths in wiring graphic data for wiring masks including vertical and horizontal wirings and slanted wirings created from layout data for semiconductor integrated circuit designing, the apparatus comprising:

an edge extraction unit extracting vertical and horizontal wiring edges and slanted wiring edges from overall wiring graphics;

a wiring width classification unit executing a scaling process for the overall wiring graphics and classifying the wiring graphics into wiring width ranges which are divided by a predefined reference wiring width;

a vertical and horizontal wiring edge extraction unit extracting the vertical and horizontal wiring edges which are in contact with graphics classified into the wiring width ranges;

a vertical and horizontal wiring interval verification unit verifying intervals between the vertical and horizontal wiring edges and opposed edges to be verification counterparts based on a vertical and horizontal reference interval for each wiring width range;

a slanted wiring edge extraction unit extracting slanted wiring edges which are in contact with graphics classified into the wiring width ranges;

a slanted wiring interval verification unit verifying intervals between the slanted wiring edges and opposed edges to be verification counterparts based on a slanted reference interval for each wiring width range;

a minimum wiring width extraction unit extracting wiring graphics less than a predefined minimum wiring width through a scaling process for the overall wiring graphics;

a minimum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are in contact with the slanted wiring edges out of the wiring graphics less than the minimum width, the minimum wiring width verification unit outputting minimum wiring width errors;

a maximum wiring width extraction unit extracting wiring graphics greater than predefined maximum width through a scaling process for the overall wiring graphics; and

a maximum wiring width verification unit extracting vertical and horizontal wiring graphics which are in contact with the vertical and horizontal wiring edges and slanted wiring graphics which are contact with the slanted wiring edges out of the wiring graphics greater than the maximum width, the maximum wiring width verification unit outputting maximum wiring width errors.

The above and other objects, aspects, features and advantages of the present invention will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A and 1B are block diagrams of a system structure where a wiring graphic verification process of the invention is executed;

FIG. 2 is a schematic diagram of a hardware environment of a computer to which a wiring graphic verification apparatus of FIGS. 1A and 1B is applied;

FIG. 3 is an operation schematic diagram of semiconductor integrated circuit design including wiring graphic verification according to the invention;

FIGS. 4A and 4B are schematic diagrams of design rules used in wiring graphic verification of the invention;

FIG. 5 is a flowchart of a wiring interval verification process according to the invention;

FIG. 6 is a schematic diagram of an example of wiring graphics which are to be verification targets of the invention;

FIG. 7 is a schematic diagram of vertical and horizontal wiring edge extraction graphics extracted from wiring graphics of FIG. 6;

FIG. 8 is a schematic diagram of slanted wiring edge extraction graphics extracted from wiring graphics of FIG. 6;

FIGS. 9A and 9B schematic diagrams of wiring graphics and edges graphics for vertical and horizontal wiring in the invention;

FIGS. 10A and 10B are schematic diagrams of a graphic data format which is input into a verification process;

FIGS. 11A and 11B are schematic diagrams of a graphic data structure and an edge data structure for vertical and horizontal wiring;

FIGS. 12A and 12B are schematic diagrams of wiring graphics and edge graphics for slanted wiring in the invention;

FIGS. 13A and 13B are schematic diagrams of a graphic data structure and an edge data structure for slanted wiring;

FIG. 14A to 14C are schematic diagrams of a scaling process which eliminates wiring graphics less than wiring width reference value a1;

FIGS. 15A and 15B are schematic diagrams of vertical and horizontal wiring interval verification targeting graphics with wiring width not greater than a1 and graphics with wiring width ranging from a1 to a2;

FIGS. 16A to 16B are schematic diagrams of slanted wiring interval verification targeting graphics with wiring width not greater than A1 and graphics with wiring width ranging From A1 to A2;

FIG. 17 is a schematic diagram of graphics with wiring width not greater than a1 extracted from the overall wiring graphics of FIG. 6;

FIG. 18 is a schematic diagram of graphics with wiring width ranging from a1 to a2 extracted from the overall wiring graphics of FIG. 6;

FIG. 19 is a schematic diagram of b1 interval verification graphics targeting vertical and horizontal wiring graphics with wiring width not greater than a1;

FIG. 20 is a schematic diagram of b2 interval verification graphics targeting vertical and horizontal wiring graphics with wiring width ranging from a1 to a2;

FIG. 21 is a schematic diagram of B1 interval verification graphics targeting slanted wiring graphics with wiring width not greater than A1;

FIG. 22 is a schematic diagram of B2 interval verification graphics targeting slanted wiring graphics with wiring width ranging from A1 to A2;

FIGS. 23A and 23B are flowcharts of a wiring width verification process according to the invention;

FIG. 24 is a schematic diagram of a scaled S graphic in which wiring graphics less than minimum width of wiring are eliminated by a scaling process to wiring graphics of FIG. 6;

FIG. 25 is a schematic diagram of extracted T graphics obtained by eliminating scaled S graphics of FIG. 24 from overall wiring graphics of FIG. 6;

FIG. 26 is a schematic diagram of graphics less than minimum width in which vertical and horizontal wiring contacting with vertical and horizontal wiring edges of FIG. 8 are extracted from extracted T graphics of FIG. 25;

FIG. 27 is a schematic diagram of scaled U graphics greater than maximum width of wiring extracted by a scaling process to wiring graphics of FIG. 6;

FIG. 28 is a schematic diagram of maximum width over graphics in which vertical and horizontal wiring contacting with vertical and horizontal wiring edges of FIG. 8 are extracted from a scaled U graphic of FIG. 27;

FIG. 29 is a flowchart of another embodiment of a wiring width verification process according to the invention;

FIG. 30 is a flowchart of a wiring width verification process of vertical and horizontal wiring in FIG. 29; and

FIG. 31 is a flowchart of a wiring width verification process of slanted wiring in FIG. 29.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIGS. 1A and 1B are block diagrams of a system structure where a wiring graphic verification process of the invention is executed. In FIGS. 1A and 1B, a system where the wiring graphic verification process of the invention is executed consists of a wiring graphic verification apparatus 10, an input apparatus 12, an output apparatus 14 and an internal memory device 16 of the wiring graphic verification apparatus 10.

The input apparatus 12 is provided with a layout data input unit 18 and a DRC rule input unit 20. The layout data input unit 18 inputs layout data for which the design process is completed and stores it into a layout data memory unit 50 of the internal memory device 16.

The DRC rule input unit 20 inputs DRC rules which are execution information to execute design rule checks of the wiring graphics generated from the input layout data, and stores it into a DRC rule memory unit 52.

The wiring graphic verification apparatus 10 is provided with a control unit 22 and a DRC execution unit 24. The DRC execution unit 24 is provided with a wiring interval verification unit 26 and a wiring width verification unit 28 in order to execute verification processes of the wiring intervals and the wiring widths for the wiring graphics in which the vertical and horizontal wiring and the slanted wiring are mixed, according to the invention.

The wiring interval verification unit 26 is provided with an edge extraction unit 30-1, a wiring width classification unit 32, a vertical and horizontal wiring edge extraction unit 34, a vertical and horizontal wiring interval verification unit 36, a slanted wiring edge extraction unit 38 and a slanted wiring interval verification unit 40, as functions achieved by the program control.

Also, the wiring width verification unit 28 is provided with an edge extraction unit 30-2, a minimum wiring width extraction unit 42, a minimum wiring width verification unit 44, a maximum wiring width extraction unit 46 and a maximum wiring width verification unit 48.

In this point, the edge extraction units 30-1, 30-2 provided to the wiring interval verification unit 26 and the wiring width verification unit 28 are the same units, and if the process is started from the wiring interval verification unit 26, it is possible to use the extraction result of the edge extraction units 30-1 in the wiring width verification unit 28 directly, therefore only the edge extraction unit in which the verification is started first is enabled.

Corresponding to these process functions of the DRC execution unit 24, the internal memory device 16 is provided with a verification target graphic memory unit 54 and an error pattern data memory unit 55 which stores error pattern data obtained from the verification result. Also, the output apparatus 14 is provided with an error pattern data display unit 56 which displays error pattern data obtained as the verification result of the DRC execution unit 24.

The process details of each function unit provided to the wiring interval verification unit 26 of the DRC execution unit 24 are as follows. The edge extraction unit 30-1 extracts vertical and horizontal wiring edges and slanted wiring edges from the overall wiring graphics which are the verification target. The wiring width classification unit 32 performs scaling of the overall wiring graphics and classifies wiring graphics into predefined wiring width ranges divided by the reference wiring width.

The vertical and horizontal wiring edge extraction unit 34 extracts the vertical and horizontal wiring edges which contact with the wiring graphics classified into the wiring width ranges. The vertical and horizontal wiring interval verification unit 36 verifies the interval between the vertical and horizontal wiring edge and an opposed edge which is the verification counterpart based on the vertical and horizontal reference interval for each wiring width range.

The slanted wiring edge extraction unit 38 extracts the slanted wiring edges which contact with the wiring graphics classified into the wiring width ranges. The slanted wiring interval verification unit 40 verifies the interval between the slanted wiring edge and an opposed edge which is the verification counterpart based on the slanted reference interval for each wiring width range.

On the other hand, the process details of each function unit of the wiring width verification unit 28 are as follows. The edge extraction unit 30-2 is the same as the edge extraction unit 30-1 of the wiring interval verification unit 26, and in practice, the vertical and horizontal wiring edges and the slanted wiring edges extracted by the edge extraction unit 30-1 from the overall wiring graphics are directly used as the extraction results.

The minimum wiring width extraction unit 42 extracts wiring graphics less than the minimum wiring width predefined in advance from the vertical and horizontal wiring and the slanted wiring by the scaling process to the overall wiring graphics. The minimum wiring width verification unit 44 extracts the vertical and horizontal wiring graphics which contact with the vertical and horizontal wiring edges and the slanted wiring graphics which contact with the slanted wiring edges out of the wiring graphics less than minimum wiring width, and outputs minimum wiring errors.

The maximum wiring width extraction unit 46 extracts wiring graphics greater than the predefined maximum wiring width from the vertical and horizontal wiring and the slanted wiring respectively, by the scaling process to the overall wiring graphics. The maximum wiring width verification unit 48 extracts the vertical and horizontal wiring graphics which contact with the vertical and horizontal wiring edges and the slanted wiring graphics which contact with the slanted wiring edges out of the wiring graphics greater than maximum wiring width, and outputs maximum wiring errors respectively.

The wiring graphic verification apparatus 10 of the invention in FIGS. 1A and 1B is achieved by hard ware resources of a computer as shown in FIG. 2, for example. In the computer of FIG. 2, a bus 201 of CPU 200 is connected with RAM 202, a hard disk controller (software) 204, a floppy disk driver (software) 210, a CD-ROM driver (software) 214, a mouse controller 218, a keyboard controller 222, a display controller 226 and a communication board 230.

The hard disk controller 204 is connected with a hard disk drive 206 and loaded with an application program which executes the wiring graphic verification process of the invention, and calls a necessary program from the hard disk drive 206 at startup of the computer, deploys the program on RAM 202 and executes it in CPU 200.

The floppy disk driver 210 is connected with a floppy disk drive (hardware) 212 and can read from and write to a floppy disk (R). The CD-ROM driver 214 is connected with a CD drive (hardware) 216 and can read data and programs stored in CD.

The mouse controller 218 transfers input operations with the mouse 220 to CPU 200. The display controller 226 performs the display on the display unit 228. The communication board 230 uses a communication line 232 and communicates with other computers or servers.

FIG. 3 is an operation schematic diagram of a computer-aided semiconductor integrated circuit design process including layout design in which the wiring graphic verification process of the invention is executed.

In this operation of the semiconductor integrated circuit design process, first, the functional design is performed in step S1, wherein the functional structure of the overall chip is determined. Subsequently, the logical circuit design is performed in step 2, wherein circuit parameters and connections between circuits are determined. Then, the layout design is performed in step S3, wherein the arrangement of cells and wiring are conducted.

This layout design is generally performed in procedures of a cell arrangement process, an outline wiring process and a detailed wiring process. In the layout design, a layout verification is performed, targeting the layout data obtained when the arrangement of cells and wiring are completed, and in this layout verification, the verifications of the wiring intervals and the wiring widths are performed, targeting the wiring graphics in which the vertical and horizontal wiring and the slanted wiring are mixed, with the design rule check (DRC) according to the invent